参数资料
型号: TS80C51RA2-VCE
厂商: Atmel
文件页数: 34/84页
文件大小: 0K
描述: IC MCU 8BIT 256BYTE 40MHZ 44VQFP
标准包装: 160
系列: 80C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40/30MHz
连通性: UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器类型: ROMless
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 内部
工作温度: 0°C ~ 70°C
封装/外壳: 44-QFP
包装: 托盘
2007-2012 Microchip Technology Inc.
DS70292G-page 41
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
4.2.5
X AND Y DATA SPACES
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, though the
implemented memory locations vary by device.
4.2.6
DMA RAM
Every dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 device contains
up to 2 Kbytes of dual ported DMA RAM located at
the end of Y data space, and is part of Y data space.
Memory locations in the DMA RAM space are
accessible simultaneously by the CPU and the DMA
controller module. DMA RAM is utilized by the DMA
controller to store data to be transferred to various
peripherals using DMA, as well as data transferred
from various peripherals using DMA. The DMA RAM
can be accessed by the DMA controller without
having to steal cycles from the CPU.
When the CPU and the DMA controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
4.3
Memory Resources
Many useful resources related to Memory Organization
are provided on the main product page of the Microchip
web site for the devices listed in this data sheet. This
product page, which can be accessed using this link,
contains the latest updates and additional information.
4.3.1
KEY RESOURCES
Section 2. “Program Memory” (DS70203)
Code Samples
Application Notes
Software Libraries
Webinars
All related dsPIC33F/PIC24H Family Reference
Manuals Sections
Development Tools
Note:
DMA RAM can be used for general
purpose data storage if the DMA function
is not required in an application.
Note:
In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
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