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参数资料
| 型号： | TS86101G2BCGL |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 10-BIT DAC, CBGA255 |
| 封装： | HERMETIC SEALED, CERAMIC, BGA-255 |
| 文件页数： | 17/57页 |
| 文件大小： | 1030K |
| 代理商： | TS86101G2BCGL |
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24
0992D–BDC–04/09
TS86101G2B
e2v semiconductors SAS 2009
6.2
Power-up Asynchronous Reset/Synchronization of Several TS86101G2B Devices
A power-on asynchronous reset is integrated on the MUXDAC. It is active during the V
EED ramp-up, (up
to 50% of its final steady-state value – V
EEA/VEED <–2.5V).
To make sure that initialization is effective, the clock should not toggle before V
EED/VEEA exceed 90% of
their final value.
This asynchronous reset allows correct initialization of the divide/4 timing circuitry that drives the 4:1
MUX, therefore providing synchronous DSP output clock signals (DSP_CK_T,DSP_CK_F) and synchro-
nous analog output signals between multiple DACs.
During the power-up reset phase, the applied (CW_IN_T,CW_IN_F) master clock should not toggle.
For initialization, three clock input configurations are authorized:
Differential clock input: the master clock can start indifferently at a logical high or low.
Single-ended clock input on CW_IN_T: the master clock must be at a logical high during reset and
start with a falling edge.
Single-ended clock input on CW_IN_F: the master clock must be at a logical low during reset and
start with a rising edge.
In all cases, the first pulse width of the master clock should last at least 100 ps and should not toggle in
an undetermined way in order to avoid metastability of the clock.
For DSP systems that require several MUXDACs to be synchronized, the following design and protocol
rules apply:
1.
The MUXDACs must be powered-up under DSP executive control, with their clocks kept inac-
tive. If used in differential mode (recommended), the clocks should be previously set to either a
high or low state, and in any case the clocks should not be toggling.
2.
A delay equalling the settling time of the power supplies (time until they reach at least 90% of
their steady state) must be respected before proceeding to step 3.
3.
The MUXDAC clocks can then be commanded to their active state. In order to reduce the prob-
ability of clock meta-stability, the first pulse should last at least 100 ps and should not toggle in
an undetermined way.
4.
All MUXDAC clock paths within a given DSP should be designed according to the standard
high-speed design rules.
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相关代理商/技术参数 |
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