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参数资料
| 型号： | TSA1005I-40IF |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | ADC |
| 英文描述： | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封装： | 7 X 7 MM, TQFP-48 |
| 文件页数： | 6/22页 |
| 文件大小： | 540K |
| 代理商： | TSA1005I-40IF |
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TSA1005 APPLICATION NOTE
14/22
NO
T
FOR
NEW
DESI
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DETAILED INFORMATION
The TSA1005 is a dual-channel, 10-bit resolution
analog to digital converter based on a pipeline
structure and the latest deep sub micron CMOS
process to achieve the best performances in
terms of linearity and power consumption.
Each channel achieves 10-bit resolution through
the pipeline structure. A latency time of 7 clock pe-
riods is necessary to obtain the digitized data on
the output bus.
The input signals are simultaneously sampled on
both channels on the rising edge of the clock. The
output data is valid on the rising edge of the clock
for I channel and on the falling edge of the clock
for Q channel. The digital data out from the differ-
ent stages must be time delayed depending on
their order of conversion. Then a digital data cor-
rection completes the processing and ensures the
validity of the ending codes on the output bus.
The structure has been specifically designed to
accept differential signals.
The TSA1005 is pin to pin compatible with the
dual 12bits/20Msps TSA1204 and the dual 12bits/
40Msps TSA1203.
COMPLEMENTARY FUNCTIONS
Some functionalities have been added in order to
simplify as much as possible the application
board. These operational modes are described as
followed.
Output Enable (OEB)
When set to low level (VIL), all digital outputs
remain active and are in low impedance state.
When set to high level (VIH), all digital outputs
buffers are in high impedance state while the
converter goes on sampling. When OEB is set to a
low level again, the data are then present on the
output with a very short Ton delay.
Therefore, this allows the chip select of the device.
The timing diagram summarizes this functionality.
In order to remain in the normal operating mode,
this pin should be grounded through a low value of
resistor.
SELECT
The digital data out from each ADC core are mul-
tiplexed together to share the same output bus.
This prevents from increasing the number of pins
and enables to keep the same package as single
channel ADC like TSA1002.
The selection of the channel information is done
through the "SELECT" pin. When set to high level
(VIH), the I channel data are present on the bus
D0-D9. When set to low level (VIL), the Q channel
data are on the output bus D0-D9.
Connecting SELECT to CLK allows I and Q chan-
nels to be simultaneously present on D0-D9; I
channel on the rising edge of the clock and Q
channel on the falling edge of the clock. (see tim-
ing diagram page 2).
REFERENCES AND COMMON MODE
CONNECTION
VREFM must be always connected externally.
Internal reference and common mode
In the default configuration, the ADC operates with
its own reference and common mode voltages
generated by its internal bandgap. VREFM pins
are connected externally to the Analog Ground
while VREFP (respectively INCM) are set to their
internal voltage of 0.88V (respectively 0.46V). It is
recommended to decouple the VREFP and INCM
in order to minimize low and high frequency noise
(refer to Figure 1)
Figure 1: Internal reference and common mode
setting
TSA1005
VIN
VINB
VREFM
VREFP
330pF
4.7uF
10nF
INCM
330pF
4.7uF
10nF
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