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参数资料
| 型号： | TSC102IDT |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封装： | ROHS COMPLIANT, PLASTIC, TSSOP-8 |
| 文件页数： | 22/24页 |
| 文件大小： | 0K |
| 代理商： | TSC102IDT |
TSC102
Electrical characteristics
Doc ID 16754 Rev 1
7/24
Table 9.
Signal conditioning amplifier
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Vicm
Common mode voltage range
Tmin < Tamb < Tmax
0Vcc
VIO
Input offset voltage
Va2 =1V
Tamb =25° C
-40° C < Tamb < 150° C
±3.5
±4.5
mV
ΔVIO
Input offset voltage drift
Tmin < Tamb < Tmax
5V/°C
Iib
Input bias current
Va2 =Va3 =VCC/2
10
pA
Voh2
Output high-level saturation
voltage (Voh2 =VCC-Vout)
Va2 =1V Va3 =0V Iout =1mA
-40° C< Tamb < 125° C
85
185
mV
Vol2
Output low-level saturation voltage
Va2 =0V Va3 =1V
Iout =1mA
-40° C< Tamb < 125° C
75
165
mV
Isc2
Short-circuit current
Out connected to VCC or Gnd
12
30
mA
ΔVout/ΔIout Output stage load regulation
-10 mA < Iout < +10 mA
Va2 =1V
Iout sink or source current
300
V/mA
CMR2
DC common mode rejection
Variation of VIO versus Vicm
Tmin < Tamb < Tmax
0V<Va2<3 V
0V<Va2<5 V
70
60
95
80
dB
SVR2
Supply voltage rejection
Variation of VIO versus VCC
3.5 V<VCC<5.5 V
Va2 =1V
-40° C < Tamb < 125° C
85
105
dB
GBP
Gain bandwidth product
RL =10kΩ, Cload =100 pF,
f=100kHz
1MHz
PM
Phase margin
RL =10kΩ, Cload = 100 pF
65
deg
SR
Slew rate
RL =10kΩ, Cload =100 pF
Va2 = 0.5 V to 4.5 V
A3 connected to OUT (follower
configuration)
Slew rate measured from 10%
to 90% of Vout step
0.2
0.4
V/s
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