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参数资料
| 型号： | TSC21020F-20SA |
| 英文描述： | IC CYCLONE III FPGA 25K 256 UBGA |
| 中文描述： | 数字信号处理器| 32位|的CMOS | RAD数据通信硬|美巡赛| 223PIN |陶瓷 |
| 文件页数： | 44/51页 |
| 文件大小： | 763K |
| 代理商： | TSC21020F-20SA |
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44
TSC21020F
4153F
–
AERO
–
06/03
where PD is power dissipation and
θ
CA
is the case-to-ambient thermal resistance. The
value of PD depends on your application; the method for calculating PD is shown under
"Power Dissipation" below.
θ
CA
varies with airflow. Table 9 shows a range of
θ
CA
values.
The TSC21020F is also available in a 256-pin MQFPF package (Ceramic). The pack-
age uses a cavity-up configuration.
Table 11.
Maximum
θ
CA
for Various Airflow Values
Airflow (m/s)
0
Power Dissipation
Total power dissipation has two components: one due to internal circuitry and one due
to the switching of external output drivers. Internal power dissipation is dependent on
the instruction execution sequence and the data values involved. Internal power dissipa-
tion is calculated in the following way:
P
INT =
I
DDIN
x V
DD
The external component of total power dissipation is caused by the switching of output
pins. Its magnitude depends on:
1) the number of output pins that switch during each cycle(O),
2) the maximum frequency at which they can switch (f),
3) their load capacitance (C), and
4) their voltage swing (V
DD
).
It is calculated by:
P
EXT =
O x C x V
DD
The load capacitance should include the processor
’
s package capacitance (C
IN
). The
switching frequency includes driving the load high and then back low. Address and data
pins can drive high and low at a maximum rate of 1/(2t
CK
). The write strobes can switch
every cycle at a frequency of 1/tCK. Select pins switch at 1/(2t
CK
), but 2 DM and 2 PM
selects can switch on each cycle. If only one bank is accessed, no select line will switch.
2
x f
Example:
Estimate P
EXT
with the following assumptions:
A system with one RAM bank each of PM (48 bits) and DM (32 bits).
32 K x 8 RAM chips are used, each with a load of 10 pF.
Single-precision mode is enabled so that only 32 data pins can switch at once.
PM and DM writes occur every other cycle, with 50% of the pins switching.
The instruction cycle rate is 20 MHz (t
CK
= 50 ns) and V
DD
= 5.0V.
0.5
1
1.5
MQFPF
31.5
°
C/W
25
°
C/W
21.5
°
C/W
19
°
C/W
CPGA
14.5
°
C/W
11.2
°
C/W
8.8
°
C/W
7.8
°
C/W
Note:
θ
JC
is 1
°
C/W for CPGA.
θ
JC
is 0.3
°
C/W for MQFPF.
Maximum recommended T
J
is 130
°
C.
As per method 1012 MIL-STD-883. Ambient temperature: 25
°
C. Power: 3.5W.
相关PDF资料 |
PDF描述 |
|---|---|
| TSC21020F-20SA-E | IC CYCLONE III FPGA 40K 324FBGA |
| TSC21020F-20SAP833 | FPGA, CYCLONE III, 40K LE, 324FBGA Programmable Logic Type:FPGA; Logic IC function:FPGA; Logic IC family:Cyclone III; Logic IC Base Number:3; I/O lines, No. of:195; |
| TSC21020F-20SASB | IC CYCLONE III FPGA 40K 324 FBGA |
| TSC21020F-20SASC | IC CYCLONE III FPGA 40K 484FBGA |
| TSC21020F-20SASL1 | IC CYCLONE III FPGA 40K 484FBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSC21020F-20SA/883 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC |
| TSC21020F-20SA-E | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC |
| TSC21020F-20SAP833 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC |
| TSC21020F-20SASB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC |
| TSC21020F-20SASC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC |
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