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参数资料
| 型号： | TSC21020F-20SASB |
| 英文描述： | IC CYCLONE III FPGA 40K 324 FBGA |
| 中文描述： | 数字信号处理器| 32位|的CMOS | RAD数据通信硬|美巡赛| 223PIN |陶瓷 |
| 文件页数： | 45/51页 |
| 文件大小： | 763K |
| 代理商： | TSC21020F-20SASB |
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45
TSC21020F
4153F
–
AERO
–
06/03
The P
EXT
equation is calculated for each class of pins that can drive:
A typical power consumption can now be calculated for this situation by adding a typical
internal power dissipation:
P
TOTAL
= P
EXT
+ (5V x I
DDIN
(typ)) = 0.210 + 1.15
= 1.36W
Note that the conditions causing a worst case P
EXT
are different from those causing a
worst case P
INT
. Maximum P
INT
cannot occur while 100% of the output pins are switch-
ing from all ones to all zeros. Also note that it is not common for a program to have
100% or even 50% of the outputs switching simultaneously.
Power and Ground
Guidelines
To achieve its fast cycle time, including instruction fetch, data access, and execution,
the TSC21020F is designed with high speed drivers on all output pins. Large peak cur-
rents may pass through a circuit board
’
s ground and power lines, especially when many
output drivers are simultaneously charging or discharging their load capacitances.
These transient currents can cause disturbances on the power and ground lines. To
minimize these effects, the TSC21020F provides separate supply pins for its internal
logic (IGND and IVDD) and for its external drivers (EGND and EVDD).
All GND pins should have a low impedance path to ground. A ground plane is required
in TSC21020F systems to reduce this impedance, minimizing noise.
The EVDD and IVDD pins should be bypassed to the ground plane using approximately
14 high-frequency capacitors (0.1
μ
F ceramic). Keep each capacitor
’
s lead and trace
length to the pins as short as possible. This low inductive path provides the TSC21020F
with the peak currents required when its output drivers switch. The capacitors
’
ground
leads should also be short and connect directly to the ground plane. This provides a low
impedance return path for the load capacitance of the TSC21020F
’
s output drivers.
If a V
DD
plane is not used, the following recommendations apply. Traces from the + 5V
supply to the 10 EVDD pins should be designed to satisfy the minimum V
DD
specifica-
tion while carrying average dc currents of [I
DDEX
/10 x (number of EVDD pins per trace)].
I
DDEX
is the calculated external supply current. A similar calculation should be made for
the four IVDD pins using the I
DDIN
specification. The traces connecting +5V to the IVDD
pins should be separate from those connecting to the EVDD pins.
A low frequency bypass capacitor (20
μ
F tantalum) located near the junction of the
IVDD and EVDD traces is also recommended.
Pin Type
# Pins
% Switch
xC
xf
xV
DD
2
P
EXT
PMA
PMS
PMWR
PMD
DMA
DMS
DMWR
DMD
15
2
1
32
15
2
1
32
50
0
-
50
50
0
-
50
68 pF
68 pF
68 pF
18 pF
48 pF
48 pF
48 pF
18 pF
5 MHz
5 MHz
10 MHz
5 MHz
5 MHz
5 MHz
10 MHz
5 MHz
25V
25V
25V
25V
25V
25V
25V
25V
0.064W
0.000W
0.017W
0.036W
0.045W
0.000W
0.012W
0.036W
P
EXT
= 0.210W
相关PDF资料 |
PDF描述 |
|---|---|
| TSC21020F-20SASC | IC CYCLONE III FPGA 40K 484FBGA |
| TSC21020F-20SASL1 | IC CYCLONE III FPGA 40K 484FBGA |
| TSC21020F-20SASL2 | IC CYCLONE III FPGA 40K 484 FBGA |
| TSC21020F-20SASL3 | IC CYCLONE III FPGA 40K 780FBGA |
| TSC21020F-20SB | IC CYCLONE III FPGA 40K 780FBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSC21020F-20SASC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC |
| TSC21020F-20SASL1 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC |
| TSC21020F-20SASL2 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC |
| TSC21020F-20SASL3 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP|32-BIT|CMOS| RAD HARD|PGA|223PIN|CERAMIC |
| TSC21020F-20SB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP|32-BIT|CMOS| RAD HARD|QFL|256PIN|CERAMIC |
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