参数资料
型号: TSC21020F-20SBSL2
英文描述: IC CYCLONE III FPGA 40K 484 UBGA
中文描述: 数字信号处理器| 32位|的CMOS | RAD数据通信硬| QFL | 256PIN |陶瓷
文件页数: 23/51页
文件大小: 763K
代理商: TSC21020F-20SBSL2
23
TSC21020F
4153F
AERO
06/03
DMBANK3
Data memory bank 3 upper boundary
DMADR
(1)
Copy of last data memory address
PMWAIT
Wait state and page size control for program memory
PMBANK1
Program memory bank 1 upper boundary
PMADR
(1)
Copy of last program memory address
System Register
MODE1
Mode control bits for bit-reverse, alternate registers, interrupt nesting and
enable, ALU saturation, floating-point rounding mode and boundary
MODE2
Mode control bits for interrupt sensitivity, cache disable and freeze, timer
enable, and I/O flag configuration
IRPTL
Interrupt latch
IMASK
Interrupt mask
IMASKP
Interrupt mask pointer (for nesting)
ASTAT
Arithmetic status flags, bit test, I/O flag values, and compare accumulator
STKY
Sticky arithmetic status flags, circular buffer overflow flags, stack status flags
(not sticky)
USTAT1
User status register 1
USTAT2
User status register 2
Note:
1. Read-only
Refer to User
s Manual for bit-level definitions of each register.
Table 6.
ALU Compute Operations
Fixed-Point
Floating-Point
Rn = Rx + Ry
Fn = Fx + Fy
Rn = Rx - Ry
Fn = Fx - Fy
Rn = Rx + Ry, Rm = Rx - Ry
Fn = Fx + Fy, Fm = Fx - Fy
Rn = Rx + Ry + CI
Fn = ABS (Fx + Fy)
Rn = Rx - Ry + CI - 1
Fn = ABS (Fx - Fy)
Rn = (Rx + Ry)/2
Fn = (Fx + Fy)/2
COMP(Rx, Ry)
COMP(Fx, Fy)
Rn = -Rx
Fn = -Fx
Rn = ABS Rx
Fn = ABS Fx
Rn = PASS Rx
Fn = PASS Fx
Rn = MIN(Rx, Ry)
Fn = MIN(Fx, Fy)
Rn = MAX(Rx, Ry)
Fn = MAX(Fx, Fy)
Table 5.
Universal Registers (Continued)
Name
Function
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