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参数资料
| 型号： | TVP5040CPFP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 颜色信号转换 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封装： | POWER, PLASTIC, TQFP-80 |
| 文件页数： | 15/109页 |
| 文件大小： | 568K |
| 代理商： | TVP5040CPFP |
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1–5
1.7
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
Analog Video
VI–1A
VI–1B
VI–2A
VI–2B
5
4
10
11
I
Analog video inputs. Up to four composite inputs or two S-video inputs or a combination of the two. The inputs
must be ac-coupled. The recommended coupling is 0.1
F.
Clock Signals
PCLK
27
O
Pixel clock output. The frequency is 12.2727 MHz for square-pixel NTSC, 14.75 MHz for square-pixel PAL,
and 13.5 MHz for ITU-R.BT.601 sampling modes.
PREF
26
I/O
Clock phase reference signal. This signal qualifies clock edges when SCLK is used to clock data that is
changing at the pixel clock rate.
SCLK
25
O
System clock output with twice the frequency of the pixel clock (PCLK).
XTAL1
XTAL2
35
36
I
External clock reference. The user may connect XTAL1 to a TTL-compatible oscillator or to one terminal of
a crystal oscillator. The user may connect XTAL2 to the other terminal of the crystal oscillator or not connect
XTAL2 at all. One single 14.31818-MHz crystal or oscillator is needed for square pixel sampling and ITU-R
BT.601 sampling.
Digital Video
UV[9:0]
62, 61,
60, 59,
58, 56,
55, 53,
52, 51
I/O
10-bit digital chrominance outputs. These terminals may also be configured to output the data from the
channel 2 A/D converter. A vendor modifiable subsystem ID may be initialized by configuring the UV[9:0]
terminals with pullup/pulldown resistors. Terminals UV[7:0] are used to set the lower byte of the subsystem
ID, and terminals UV[9:8] are used to set the bit 9 and bit 8. During reset, UV[9:0] terminals are used to set
the VIP device configuration registers.
Y[9:0]
50, 49,
48, 46,
45, 43,
42, 41,
40, 39
I/O
10-bit digital luminance outputs, or 10-bit multiplexed luminance and chrominance outputs. These terminals
may also be configured to output the data from the channel 1 A/D converter. A vendor modifiable subsystem
ID may be initialized by configuring the Y[9:0] terminals with pullup/pulldown resistors. Terminals Y[7:0] are
used to set the upper byte of the subsystem ID, and terminals Y[9:8] are used to set the bit 11 and bit 10. During
reset, Y[9:0] terminals are used to set the VIP device configuration registers.
HOST PORT-Bus
A[1:0]
74, 73
I
PHI mode: PHI address port.
VIP mode: During reset A[1:0] terminals are input and are used to set the VIP device configuration registers.
A[1:0] are used to set bits 13 and 12 of the subsystem device ID. Pull up on each terminal during
reset will set a 1 to the corresponding bit . Leaving the terminal undriven or pulldown on the
terminal during the reset will set a 0. The internal weak pulldown remains on after reset.
D[7:0]
72, 71,
70, 69,
67, 66,
64, 63
I/O
PHI mode: PHI data port-bit [7:0]
VIP mode: During reset, D[7:0] terminals are input and are used to set the VIP device configuration registers.
D[7:0] are used to set the lower byte of the subsystem device ID. Pull up on each terminal during
reset will set a 1 to the corresponding bit . Leaving the terminal undriven or pulldown on the
terminal during the reset will set a 0. The internal weak pulldown remains on after reset.
INTREQ
80
I/O
PHI mode: Interrupt request (INTREQ) Pullup is required if configured as open drain.
I2C mode: Interrupt request (INTREQ) Pullup is required if configured as open drain.
VIP mode: Interrupt request (VIRQ) No internal weak pulldown. 10 K
pullup resistor is required.
VC0
79
I/O
PHI mode: PHI port data acknowledgement or ready signal (DTACK)
I2C mode: Serial clock (SCL) Pullup is required.
VIP mode: Hardware address bit 0 (HAD[0])
VC1
78
I/O
PHI mode: PHI port read-write or write (RW/WR)
I2C mode: Serial data (SDA) Pullup is required.
VIP mode: Hardware address bit 1 HAD[1] 10-K
pullup resistor is required.
VC2
77
I/O
PHI mode: PHI port data strobe or read signal (DS/RD)
VIP mode: Hardware control (HCTL) 10-K
pullup resistor is required.
VC3
76
I
PHI mode: PHI port chip select (VC)
I2C mode: Slave address select (I2CA)
VIP mode: VIPCLK
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