参数资料
型号: TVP5040CPFP
厂商: TEXAS INSTRUMENTS INC
元件分类: 颜色信号转换
英文描述: COLOR SIGNAL DECODER, PQFP80
封装: POWER, PLASTIC, TQFP-80
文件页数: 17/109页
文件大小: 568K
代理商: TVP5040CPFP
1–7
1.7
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
Sync Signals (Continued)
HSYN
30
O
Horizontal sync signal with respect to the digital video data output. The rising edge time is programmable
via the host port.
PALI
32
I/O
PAL line indicator or horizontal lock indicator.
For PAL line indicator, a logic 1 indicates a noninverted line, and a logic 0 indicates an inverted line. For
horizontal lock indicator, a logic 1 indicates the internal horizontal PLL is in a locked state.
This terminal is an input terminal during reset and is used in conjunction with GLCO and FID to select the
mode of the host interface. During reset, this terminal can be pulled up to set a 1, or pulled down to set a 0.
VSYN
29
O
Vertical sync signal with respect to the digital video data output.
1.8
Strapping Terminals Description
All of the following terminals have reset strapping options. The states of these terminals are sampled during reset
to configure TVP5040 for various modes of operation. These terminals are temporarily turned into inputs with weak
internal pulldown (approximately 40-K
resistor) during reset and return to their normal operation after reset. Each
of the following terminals can be pulled up with a 10-K
resistor to set a 1 to the corresponding bit or be left undriven
during reset, relying on the internal pulldown resistor to pull the terminal low to set a 0 to the corresponding bit.
TERMINAL
DESCRIPTION
NAME
NO.
DESCRIPTION
UV[7:0]
60, 59, 58, 56
55, 53, 52, 51
Lower byte of VIP subsystem vendor ID (VIP register 004)
Y[7:0]
48, 46, 45, 43,
42, 41, 40, 39
Upper byte of VIP subsystem vendor ID (VIP register 005)
D[7:0]
72, 71, 70, 69,
67, 66, 64, 63,
Lower byte of VIP subsystem device ID (VIP register 006)
UV[9:8]
62, 61
Bits 1 and 0 of the upper byte of VIP subsystem device ID (VIP register 007)
Y[9:8]
50, 49
Bits 3 and 2 of the upper byte of VIP subsystem device ID (VIP register 007)
HSYN
30
Bit 4 of the upper byte of VIP subsystem device ID (VIP register 007)
VSYN
29
Bit 5 of the upper byte of VIP subsystem device ID (VIP register 007)
A[1:0]
74, 73
Bits 7 and 6 of the upper byte of VIP subsystem device ID (VIP register 007)
AVID
28
Y, U/V output enable (bit 4) and HSYN, VSYN, AVID, FID, and PALI output enable (bit 3) of miscellaneous
control ( register 03)
PREF
26
Clock enable bit (bit 0) of miscellaneous control (register 03)
FID
33
Host interface mode (see Table 2-2)
PALI
32
Host interface mode (see Table 2-2)
GLCO
31
Host interface mode (see Table 2-2)
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