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参数资料
| 型号： | TVP5146M2PFPG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 颜色信号转换 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封装： | GREEN, PLASTIC, HTQFP-80 |
| 文件页数： | 24/107页 |
| 文件大小： | 1427K |
| 代理商： | TVP5146M2PFPG4 |
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Functional Description
15
SLES141B—August 2007
TVP5146M2PFP
2.2.4 Component Video Processor
The component video processing block supports a user-selectable contrast, brightness, and saturation
adjustment in YCbCr output formats. For YCbCr output formats, gain and offset values are applied to the luma
data path in order to map the pixel values to the correct output range (for 10-bit Ymin = 64 and Ymax = 940),
and to provide a means of adjusting contrast and brightness. For Y, digital contrast (gain) and brightness
(offset) factors can vary from 0 to 255. The contrast control adjusts the amplitude range of the Y output
centered at the midpoint of the output code range. The limit block limits the output to the ITU-R BT.601 range
(Ymin to Ymax) or an extended range, depending on a user setting.
x
Gain
Y
Limit
+
Offset
Figure 210. Y Component Gain, Offset, Limit
For CbCr components, a saturation (gain) factor is applied to the CbCr inputs in order to map them to the CbCr
output code range and provide saturation control. Similarly, the limit block can limit CbCr outputs to a valid
range:
Cb,Crmin = 64 / Cb,Crmax = 960
x
Gain
CbCr
Limit
Figure 211. CbCr Component Gain, Offset, Limit
2.2.5 Color Space Conversion
The formulas for RGB to YCbCr conversion are given as:
Y = 0.299
× R + 0.587 × G + 0.114 × B
Cb = –0.172
× R – 0.339 × G + 0.511 × B + 512
Cr = 0.511
× R – 0.428 × G – 0.083 × B + 512
2.3
Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive
the PLL. This can be input to the TVP5146M2 decoder at the 1.8-V level on terminal 74 (XTAL1), or a crystal
of 14.31818-MHz fundamental resonant frequency can be connected across terminals 74 and 75 (XTAL2).
If a parallel resonant circuit is used as shown in Figure 212, then the external capacitors must have the
following relationship:
CL1 = CL2 = 2CL – CSTRAY,
where CSTRAY is the terminal capacitance with respect to ground. Figure 212 shows the reference clock
configurations. The TVP5146M2 decoder generates the DATACLK signal used for clocking data.
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| TVP5146PFPRG4 | COLOR SIGNAL DECODER, PQFP80 |
| TVP5146PFP | COLOR SIGNAL DECODER, PQFP80 |
| TVP5146PFPR | COLOR SIGNAL DECODER, PQFP80 |
| TVP5146PFPG4 | COLOR SIGNAL DECODER, PQFP80 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TVP5146M2PFPR | 功能描述:视频 IC 10B Hi Qual Sgl-Chip Dig Vid Dec RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
| TVP5146M2PFPRG4 | 制造商:Texas Instruments 功能描述: |
| TVP5146PFP | 功能描述:视频 IC 10B High Qual S-Chip Dig Vid Decoder RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
| TVP5146PFP | 制造商:Texas Instruments 功能描述:IC VIDEO DECODER 10BIT 30MSPS HTQFP-80 制造商:Texas Instruments 功能描述:IC, VIDEO DECODER, 10BIT 30MSPS HTQFP-80 |
| TVP5146PFPG4 | 制造商:Texas Instruments 功能描述:10BIT VIDEO DECODER SMD HTQFP80 |
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