参数资料
型号: TVP5146M2PFPG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 颜色信号转换
英文描述: COLOR SIGNAL DECODER, PQFP80
封装: GREEN, PLASTIC, HTQFP-80
文件页数: 45/107页
文件大小: 1427K
代理商: TVP5146M2PFPG4
Functional Description
34
SLES141B—August 2007
TVP5146M2PFP
2.11.2
AFE Gain Control Register
Subaddress
01h
Default
0Fh
7
6
5
4
3
2
1
0
Reserved
1
AGC chroma
AGC luma
Bit 3: 1 must be written to this bit.
Bit 2: 1 must be written to this bit.
AGC chroma: Controls automatic gain in the chroma/B/R/PbPr channel:
0 = Manual (if AGC luma is set to manual, AGC chroma is forced to be in manual)
1 = Enabled auto gain, applies a gain value acquired from the sync channel for S-video and component
mode. When AGC luma is set, this state is valid. (default)
AGC luma: Controls automatic gain in the embedded sync channel of CVBS, S-video, component video:
0 = Manual gain, AFE coarse and fine gain frozen to the previous gain value set by a AGC when this bit is
set to 0.
1 = Enabled auto gain applies only to the embedded sync channel (default)
These settings only affect the analog front-end (AFE). The brightness and contrast of component, CVBS
are not affected by these settings.
2.11.3
Video Standard Register
Subaddress
02h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Video standard [2:0]
Video standard [2:0]:
CVBS and S-Video
Component Video
000 = Autoswitch mode (default)
Autoswitch mode (default)
001 = (M, J) NTSC
Component 525
010 = (B, D, G, H, I, N) PAL
Component 625
011 = (M) PAL
Reserved
100 = (Combination-N) PAL
Reserved
101 = NTSC 4.43
Reserved
110 = SECAM
Reserved
111 = PAL 60
Reserved
NOTE: PAL60 is not included in autoswitch mode.
With the autoswitch code running, the user can force the decoder to operate in a particular video standard
mode by writing the appropriate value into this register. Changing these bits causes the register settings to
be reinitialized.
2.11.4
Operation Mode Register
Subaddress
03h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Power save
Power save:
0 = Normal operation (default)
1 = Power-save mode. Reduces the clock speed of the internal processor and switches off the ADCs. I2C
interface is active and all current operating settings are preserved.
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