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FEATURES
APPLICATIONS
DESCRIPTION
SLES164 – FEBBRUARY 2006
TRIPLE 8/10-BIT, 165/110 MSPS, VIDEO
AND GRAPHICS DIGITIZER WITH ANALOG PLL
LCD TV/Monitors/Projectors
Analog Channels
DLP TV/Projectors
– -6 dB to 6 dB Analog Gain
PDP TV/Monitors
– Analog Input MUXs
PCTV Set-Top Boxes
– Auto Video Clamp
Digital Image Processing
– Three Digitizing Channels, Each With
Video Capture/Video Editing
Independently Controllable Clamp, PGA,
Scan Rate/Image Resolution Converters
and ADC
Video Conferencing
– Clamping: Selectable Clamping Between
Video/Graphics Digitizing Equipment
Bottom Level and Mid-level
– Offset: 1024-Step Programmable RGB or
YPbPr Offset Control
TVP7001 is a complete solution for digitizing video
– PGA: 8-Bit Programmable Gain Amplifier
and graphic signals in RGB or YPbPr color spaces.
– ADC: 8/10-Bit 165/110 MSPS A/D Converter
The device supports pixel rates up to 165 MHz.
– Automatic Level Control Circuit
Therefore, it can be used for PC graphics digitizing
up to the VESA standard of UXGA (1600
× 1200)
– Composite Sync: Integrated Sync-on-Green
resolution at 60 Hz screen refresh rate, and in video
Extraction From GreenLuminance Channel
environments for the digitizing of digital TV formats,
– Support for DC and AC-Coupled Input
including HDTV up to 1080p. TVP7001 can be used
Signals
to digitize CVBS and S-video signal with 10-bit ADCs.
PLL
The TVP7001 is powered from 3.3-V and 1.8-V
– Fully Integrated Analog PLL for Pixel Clock
supply and integrates a triple high-performance A/D
Generation
converter with clamping functions and variable gain,
independently programmable for each channel. The
– 12-165 MHz Pixel Clock Generation From
clamping timing window is provided by an external
HSYNC Input
pulse or can be generated internally. The TVP7001
– Adjustable PLL Loop Bandwidth for
includes analog slicing circuitry on the Y or G input to
Minimum Jitter
support
sync-on-luminance
or
sync-on-green
– 5-Bit Programmable Subpixel Accurate
extraction. In addition, TVP7001 can extract discrete
Positioning of Sampling Phase
HSYNC and VSYNC from composite sync using a
sync slicer.
Output Formatter
– Support for RGB/YCbCr 4:4:4 and YCbCr
TVP7001 also contains a complete analog PLL block
to generate a pixel clock from the HSYNC input. Pixel
4:2:2 Output Modes to Reduce Board Traces
clock output frequencies range from 12 MHz to 165
– Dedicated DATACLK Output for Easy
MHz.
Latching of Output Data
All
programming
of
the
part
is
done
via
an
System
industry-standard I2C interface, which supports both
– Industry-Standard Normal/Fast I2C Interface
reading and writing of register settings. The TVP7001
With Register Readback Capability
is
available
in
a
space-saving
TQFP
100-pin
– Space-Saving TQFP-100 Pin Package
PowerPAD package.
– Thermally-Enhanced PowerPAD Package
for Better Heat Dissipation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.