参数资料
型号: UBA2024BT/N1,518
厂商: NXP Semiconductors
文件页数: 4/17页
文件大小: 0K
描述: IC DRIVER HALF BRIDGE 14SO
标准包装: 2,500
类型: CFL/TL 驱动器
频率: 40.05kHz ~ 42.68kHz
电流 - 电源: 5mA
电源电压: 11.4 V ~ 13.3 V
工作温度: -40°C ~ 150°C
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
供应商设备封装: 14-SO
包装: 带卷 (TR)
NXP Semiconductors
UBA2024
Half-bridge power IC for CFL lamps
7. Functional description
7.1 Supply voltage
The UBA2024 does not require an external low-voltage supply as the mains supply
voltage applied to pin HV powers it. The IC derives its own low supply voltage from this for
its internal circuitry.
7.2 Start-up state
With an increase of the supply voltage on pin HV, the IC enters the start-up state. In the
start-up state the high-side power transistor is not conducting and the low-side power
transistor is switched on. The internal circuit is reset and the capacitors on the bootstrap
pin FS and low-voltage supply pin V DD are charged. Pins RC and SW are switched to
ground. The start-up state is defined until V DD = V DD(startup) .
7.3 Sweep mode
The IC enters the sweep mode when the voltage on pin V DD > V DD(startup) . The capacitor
on pin SW is charged by I SW and the half-bridge circuit starts oscillating. The circuit enters
the start-up state again when the voltage on pin V DD < V DD(stop) .
The sweep time (t sweep ) is determined by the charge current (I ch(sw) ) and the external
capacitor (C SW ). Typical the total sweep time set by C SW is:
t sweep = C SW ( nF ) × 10.3 ms
(1)
During the sweep time the current flowing through the lamp electrodes performs some
preheating of the filaments. See Figure 5 .
7.4 Reset
A DC reset circuit is incorporated in the high-side driver. The high-side transistor is
switched off when the voltage on pin FS is below the high-side lockout voltage V float(UVLO) .
7.5 Oscillation
The oscillation is based upon the 555-timer function. A self oscillating circuit is made with
the external resistor R OSC and the capacitor C OSC (see Figure 4 ).
To realize an accurate 50 % duty cycle, an internal divider is used. This reduces the bridge
frequency to half the oscillator frequency.
The output voltage of the bridge will change at the falling edge of the signal on pin RC.
The design equation for the half-bridge frequency is:
f osc = -----------------------------------------
1
k × R OSC × C OSC
An overview of the oscillator signal, internal LS and HS drive signals and the output is
given in Figure 4 .
(2)
UBA2024
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6.2 — 1 November 2010
? NXP B.V. 2010. All rights reserved.
4 of 17
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