参数资料
型号: UBA2071AT/N1,118
厂商: NXP Semiconductors
文件页数: 10/35页
文件大小: 0K
描述: IC DVR HALF BRIDGE 24-SOIC
标准包装: 1,000
类型: CCFL/EEFL 控制器
频率: 38 ~ 42kHz
电流 - 电源: 1.5mA
电源电压: 14V
工作温度: -25°C ~ 100°C
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SO
包装: 带卷 (TR)
其它名称: 935285776118
NXP Semiconductors
UBA2071; UBA2071A
Half bridge control IC for CCFL backlighting
When the voltage on the EN pin goes over V th(H)1(EN) after the IC has been disabled (EN
pin below V th(L)(EN) ) the IC will start up in DC blocking capacitor charging mode 3 . When
the voltage on the EN pin goes over V th(H)1(EN) after the IC has been off (EN pin below
V th(L)(EN) or V DD below V stop(VDD) ) the IC will start up in DC blocking capacitor charging
mode. When the voltage on the EN pin goes over V th(H)2(EN) the IC will continue with the
initial ignition frequency sweep and normal operation mode. Figure 6 , EN con?guration,
shows three examples of how the enable input can be used:
UBA2071
EN
R1
enable
C1
(1)
V Hv
V Hv
UBA2071
EN
R2
R4
V Cblock
UBA2071
EN
R2
R4
V Cblock
R3
(2)
Cblock
(3)
R3
R5
Cblock
disable
014aaa253
Fig 6.
EN con?guration
1. Digital enable input with DC blocking capacitor charging. R1 and C1 de?ne a ?xed
DC blocking capacitor charging time.
Remark: The digital input signal high level has to be above the maximum value of
V th(H)2(EN) .
2. Sensing of HV supply and DC blocking capacitor voltages via the EN pin. The IC will
start in DC blocking capacitor charging mode if V VDD is above V startup(VDD) and V HV is
above ( ( R2/R4 ) + ( R2/R3 ) + 1 ) × V th(H)1(EN) . It will then go into initial ignition frequency
sweep and normal operation mode once V Cblock has been charged to
( ( ( R4/R2 ) + ( R4/R3 ) + 1 ) × V th(H)2(EN) – R4/R2 × V HV ) .
3. Sensing of HV supply and DC blocking capacitor voltages via the EN pin combined
with digital enable input.
In DC blocking capacitor charging mode the low-side power switch (Q LS in Figure 3 ) is
turned on for a period ((1/f sw(max) ) ? t no ) and then the high-side power switch (Q HS in
Figure 3 ) is turned on for a period ((1/f sw(max) ) ? t no ) followed by a period of (3/f sw(min) )
during which both power switches are off. This is repeated until the mode is left. When
leaving the DC blocking capacitor charging mode by raising the EN pin above V th(H)2(EN) ,
the running cycle of the DC blocking capacitor charging mode will ?rst be completed (see
3.
When the enable input is kept high during the time that the IC is off, because the supply voltage is too low, the IC might not start in
DC blocking capacitor charging mode.
UBA2071_A_1
? NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 23 June 2008
10 of 35
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