参数资料
型号: UBA2071AT/N1,118
厂商: NXP Semiconductors
文件页数: 15/35页
文件大小: 0K
描述: IC DVR HALF BRIDGE 24-SOIC
标准包装: 1,000
类型: CCFL/EEFL 控制器
频率: 38 ~ 42kHz
电流 - 电源: 1.5mA
电源电压: 14V
工作温度: -25°C ~ 100°C
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SO
包装: 带卷 (TR)
其它名称: 935285776118
NXP Semiconductors
UBA2071; UBA2071A
Half bridge control IC for CCFL backlighting
to CCFLs
Ich(CSWP)
Idch(CSWP)
IFB
OTA
PWMD
0
1
S2
DSR
R1
Vref(creg)
UBA2071
S1
Ich(CVFB)
to VCO
CIFB
C1
CVFB
C2
CSWP
C3
014aaa106
Fig 11. Lamp frequency control circuit
Under normal operating conditions, the voltage across capacitor C2, which is connected
to the CVFB pin, will follow the voltage on the CIFB pin. During the lamps-on period of the
PWM dimming, the voltage across C3, which is connected to the CSWP pin, will follow the
voltage on the CVFB pin and therefore also the voltage on the CIFB pin.
The voltage on the CSWP pin is connected to the VCO input of the HF oscillator and thus
controls the switching frequency. If the load is assumed to be inductive an increase in the
frequency will cause a decrease in the lamp current, while a decrease in the frequency will
cause an increase in the lamp current.
The advantage of having a separate current regulation loop timing capacitor pin CIFB next
to the voltage regulation loop timing capacitor CVFB is that time constants for both loops
can be set independently. The separate PWM dimming sweep timing capacitor pin CSWP
makes it possible to set the PWM dimming sweep speed independent of the current and
voltage regulation loops.
8.11 PWM dimming
Pulse Width Modulation (PWM) dimming is a method of reducing the average lamp light
output by switching the lamps on and off with a repetition rate or PWM frequency, f PWM ,
high enough not to be seen by the human eye (but much lower than the inverter frequency
f sw ). By varying the lamp-on to lamp-off, period ratio, called the duty cycle δ PWM , the light
output can be varied over a wide range.
The voltage at the CSWP pin determines the actual switching frequency, it inverses in
proportion to the switching frequency. During the lamps-on period of the PWM dimming it
follows the voltage at the CVFB pin (the current I ch(CSWP) is drained by the tracking circuit
between the CVFB pin and the CSWP pin).
Just prior to transitioning towards the lamps-off period of the PWM dimming the lamp
current control loop, see Figure 11 , is opened by opening switches S1. The voltage on the
CSWP pin is swept down, decaying the lamp current, leading in the PWM lamp-off
situation, after which the half bridge switch actions are stopped, resulting in true zero lamp
current. see Figure 9 . In the meantime the regulation level is preserved in C1 and C2. The
UBA2071_A_1
? NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 23 June 2008
15 of 35
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