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参数资料
| 型号： | UCC1829J-1 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 2.2 A SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, CDIP20 |
| 封装： | CERDIP-20 |
| 文件页数： | 6/10页 |
| 文件大小： | 176K |
| 代理商： | UCC1829J-1 |
5
UCC1829-1/-2/-3
UCC2829-1/-2/-3
UCC3829-1/-2/-3
PIN DESCRIPTIONS
BISYNC: Combination clock output/sync input pin. The
clock signal can be viewed on this pin. If BISYNC is con-
nected to BISYNC of other UCC3829 chips, all the oscil-
lators will run at the highest of all the chips frequencies.
The BISYNC pin has a weak pull down and a strong pull
up.
CL+: Current sense input for current limiting. The CL+
and CL- pins are used for current sensing. CL+ is the
current signal while CL- is the kelvin return for the sens-
ing function.
CL–: Current sense input kelvin common.
CT: Oscillator timing capacitor. A capacitor connected
between CT and GND is charged by a current source
controlled by RT1. The capacitor is discharged through a
resistor connected between CT and RT2.
EAOUT: Error amplifier output. This output is normally
connected directly to the PWCONT pin. It can also be
connected to PWCONT through a resistor divider at-
tenuation network to allow more swing of the error ampli-
fier output. A maximum capacitive load of 20pF with
respect to ground must be observed to insure stability of
the error amplifier.
GND: Logic and analog ground. The GND pin should be
used for all signal level returns, except the current sense
inputs.
INV: Error amplifier inverting input.
LEB: Leading edge blanking programming pin. Connect-
ing a resistor between VREF and LEB and a capacitor
between LEB and GND will program a leading edge
blanking time according to the RC of the resistor/capaci-
tor combination. Connecting the LEB pin to VDD disables
the Leading Edge Blanking function.
NINV: Error amplifier non-inverting input.
OUTA: Output A. The OUTA pin will pull down with ap-
proximately 1.5A and pull up with approximately 0.75A.
The UCC3829-1 implements push-pull outputs with
OUTA and OUTB active on alternating clock cycles. The
UCC3829-2 implements OUTA and OUTB being in
phase. The UCC3829 -3 implements OUTA and OUTB to
be non-overlapping complementary outputs during the
same
clock
cycle.
The
output
frequency
of
the
UCC3829-1 is half that of the UCC3829-2
and
UCC3829 -3.
OUTB: Output B. The OUTB pin will pull down with ap-
proximately 1.5A and pull up with approximately 0.75A.
The UCC3829-1 implements push-pull outputs with
OUTA and OUTB active on alternating clock cycles. The
UCC3829-2 implements OUTA and OUTB being in
phase. The UCC3829 -3 implements OUTA and OUTB
to be non-overlapping complementary outputs during the
same
clock
cycle.
The
output
frequency
of
the
UCC3829-1 is half that of the UCC3829-2
and
UCC3829 -3.
PGND: Power ground return. The PGND pin should be
used as the return for the VDD bypass capacitor and the
current sense kelvin CL-.
PWCONT: Pulse width control input. This is connected to
the PWM comparator inverting input.
RAMP: Ramp input . This is connected to the PWM com-
parator non-inverting input through a level shifting volt-
age of approximately 1.25V.
RT1: Oscillator charging current programming resistor. A
1V reference at this pin generates a current through a re-
sistor connected between RT1 and GND. This current is
mirrored and ratioed to charge the timing capacitor con-
nected to pin CT.
RT2: Oscillator discharge time programming resistor. The
oscillator (and output) dead time can be programmed via
this pin. The discharge of the timing capacitor CT is de-
termined by an RC discharge using a resistor connected
between RT2 and CT.
SS: Soft start capacitor pin. A capacitor connected to SS
determines the time the IC takes to soft start. The nomi-
nal SS pin pull up and pull down current is 20
A. The soft
start time delay is approximately calculated as:
CSS 3V
20 A
when charging from 0V. After the SS pin reaches the SS
complete threshold of 3V, another SS cycle can be
started. The restart time is approximately:
2 CSS 3V
20 A
UVLO: Undervoltage lockout programming pin. Connect-
ing a resistor divider between VDD, UVLO, and GND
sets a VDD value at which the UCC3829 chip will be en-
abled. When the voltage on the UVLO pin reaches 3V,
the chip is enabled. When the voltage on UVLO falls be-
low 2.5V, the chip is disabled.
VDD: Voltage supply to IC. VDD is clamped at 14V.
VREF: Voltage reference output and filtering. The voltage
reference output appears on the VREF pin. It is buffered
to drive approximately 5mA and short circuit protected at
approximately 25mA. A bypass capacitor of at least
0.1
F must be connected from VREF to ground.
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