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参数资料
| 型号： | UCC1829J-1 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 2.2 A SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, CDIP20 |
| 封装： | CERDIP-20 |
| 文件页数： | 7/10页 |
| 文件大小： | 176K |
| 代理商： | UCC1829J-1 |
6
UCC1829-1/-2/-3
UCC2829-1/-2/-3
UCC3829-1/-2/-3
APPLICATION INFORMATION
Functional Programmability
Various features of the UCC3829 are user programma-
ble. RT1 and RT2 allow independent programming for
oscillator rise and fall times within the normal operational
range of the chip. A new feature allows the user to pro-
gram the voltage that flags an undervoltage fault. The
default value of 14V for chip turn-on is selected by tying
the UVLO pin to ground.
If the user wants to select
startup voltage then a resistive divider should be tied
from Vdd to ground, with the centerpoint tied to the
UVLO pin. The chip will be enabled when the UVLO pin
reaches 3V, and disabled below 2.5V.
Leading edge
blanking can also be optimized to eliminate turn-on noise
when current mode control is used or disabled when de-
sired.
Oscillator
The oscillator uses an external capacitor CT and two ex-
ternal resistors RT1 and RT2 to generate the clock fre-
quency and dead time. A precise reference voltage is
placed across resistor RT1 to generate a current refer-
ence. The current is then mirrored and used to charge
the capacitor CT from VVALLEY. When a “peak” threshold
is reached, an on chip MOSFET connects the RT2 pin to
GND, discharging CT to a “valley” threshold through an
external resistor RT2. The CT waveform has a linear
ramp shape while charging and an exponential (RC)
slope while discharging. The slope of the charging ramp
is set by the CT,RT1 combination and the slope of the
discharging ramp is set by the values of CT and RT2.
The approximate equation for the rising edge (TR)ofthe
CT waveform (maximum on-time period) is:
TC R
VV
RT
T
PEAK
VALLEY
=
1
93
–
.
The approximate equation for the falling edge (TF)ofthe
CT waveform (deadtime period) is:
TR C
V
R
V
R
FT
T
PEAK
T
VALLEY
T
==
2
1
2
1
93
ln
–
.
–
.
Assuming that:
93
2
1
2
1
..
R
V
R
V
T
PEAK
T
VALLEY
<<
and
We get a simplified equation:
TR C
V
FT
T
PEAK
VALLEY
=
2
ln
Given a maximum on-time and frequency and assuming
an initial value for either RT2 or CT, you can use the TF
equation to calculate the other. Once you have a value
for CT, you can calculate RT1 using the TR equation.
Error Amplifier Section
The Error Amplifier has both inputs and the output
brought out to pins NINV, INV, and EAOUT. The output of
the error amplifier can be connected to the inverting input
of the PWM comparator via the pin PWCONT. This al-
lows inserting attenuation which enables using the full
output swing of the error amplifier. The output of the error
amplifier is forced to follow the soft start waveform during
soft start.
PWM and Output Section
The non-inverted input of the PWM comparator is con-
nected to RAMP. The RAMP can be connected to either
the CT capacitor for voltage mode control, to the current
sense resistor for current mode control, or to a feed for-
ward capacitor for input voltage feed forward control. The
CT waveform can be coupled to RAMP to provide slope
compensation in the current mode case. The MOSFET
switch connected to RAMP provides for the discharge of
the feedforward capacitor. There is a short time constant
(3ns) filter across the inputs of the PWM comparator to
reduce noise.
The output of the PWM comparator feeds an OR gate
which, together with several other fault signals, sets the
PWM latch. The latch is in turn reset on every dead time
period of the clock waveform. The output of the PWM
latch is OR’ed with the clock and the output of the Fault
Latch (described below) to feed into the pulse steering
Toggle Flip-Flop (TFF). The resulting signal is then
steered
according
to
the
output
configuration
of
UCC3829. The clock output becomes the deadtime be-
tween the outputs.
Figure 3.
UDG-97016
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