参数资料
型号: UCC28250RGPT
厂商: Texas Instruments
文件页数: 12/53页
文件大小: 0K
描述: IC REG CTRLR PWM CM/VM 20-QFN
标准包装: 1
PWM 型: 电流/电压模式
输出数: 1
频率 - 最大: 1MHz
占空比: 100%
电源电压: 4.7 V ~ 17 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 20-VFQFN 裸露焊盘
包装: 标准包装
其它名称: 296-27777-6
SLUSA29C – APRIL 2010 – REVISED JULY 2011
A pulse signal may also be applied to the EN pin. Pulse-enable operation is shown on Figure 4 . If the EN falling
edge happens before the SS voltage reaches 0.3 V, the enable signal at EN pin is considered as a pulse. In this
case, the next rising edge at EN pin disables the controller. If the falling edge of the first pulse at EN pin happens
after SS rises to 0.3 V, the UCC28250 interprets the pulse enable as a level enable, and an external solution as
shown on Figure 5 (a) can be used to reduce the pulse width. In this circuit, R2 is used to limit the current
(especially the negative current) through the internal ESD cell. Figure 5 (b) illustrates the waveforms based on
this solution. To prevent false trigger by noises, the pulse at the EN pin must be at least 2.25 V (minimum) high
and 3 μ s wide to be considered valid.
Choose the R1, R2, and C values based on the following equations:
Choose R2 based on the current limit requirement from the device.
R 2 > 10k W
(1)
Choose R1 arbitrarily but much smaller than R2 and choose C1 according to the time constant requirement to
generate longer than 3- μ s pulse.
C 1 =
6 m s
R 1
(2)
If enable function is not used, pull EN pin to VREF.
UVLO
EN
SS
0.3V
CLK
Figure 4. Pulse Enable at EN Pin
(a)
UCC28250
(b)
Enable
Signal
C1
R2
EN
Enable
Signal
R1
EN
Figure 5. An External Solution to Generate Enable Pulses for Pulse Enable
12
Product Folder Link(s): UCC28250
Copyright ? 2010 – 2011, Texas Instruments Incorporated
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