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| 型号： | UCC2891DR |
| 厂商： | Texas Instruments |
| 文件页数： | 20/41页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBK ISO CM 16SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 74% |
| 电源电压： | 8.5 V ~ 16 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
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UCC2891, UCC2892
UCC2893, UCC2894
SLUS542F ? OCTOBER 2003 ? REVISED JULY 2009
APPLICATION INFORMATION: SETUP GUIDE
Note, that t SS defines a time interval to reach the maximum current capability of the converter and not the time
required to ramp the output voltage from 0 V to its nominal, regulated level. Using an open-loop start up scheme
does not allow accurate control over the ramp up time of the output voltage. In addition to the I SS and C SS values,
the time required to reach the nominal output voltage of the converter is a function of the maximum output
current (current limit), the output capacitance of the converter and the actual load conditions. If it is critical to
implement a tightly controlled ramp-up time at the output of the converter, the soft-start must be implemented
using a closed loop technique. Closed loop soft-start can be implemented with the error amplifier of the voltage
regulation loop when its voltage reference is ramped from 0 V to its final steady state value during the required
t SS start up time interval.
Step 3. VDD Bypass Requirements
First, the high-frequency filter capacitor is calculated based on the gate charge parameters of the external
MOSFETs. Assuming that the basic switching frequency ripple should be kept below 0.1-V across C HF , its value
can be approximated as:
C HF +
Q G(main) ) Q G(aux)
0.1 V
(13)
The energy storage requirements are defined primarily by the start up time (t SS ) and turn-on (approximately
12.7 V) and turn-off (approximately 8 V) thresholds of the controller ’s undervoltage lockout circuit monitoring
the VDD voltage at pin 14. In addition, the bias current consumption of the entire primary side control circuit (I DD
+ I EXT ) must be known. This power consumption can be estimated as:
P BIAS + I DD ) I EXT ) Q G(main) ) Q G(aux)
f SW
V DD
(14)
During start up (t SS ) this power is provided by C BIAS while its voltage must remain above the UVLO turn-off
threshold. This relationship can be expressed as:
P BIAS
2
t SS t 1
C BIAS
13 2 * 8.5 2
(15)
Rearranging the equation yields the minimum value for C BIAS :
C BIAS u
2
P BIAS t SS
13 2 * 8.5 2
(16)
Step 4. Delay Programming
From the power stage design, the required turn-on delay (t DEL ) of the gate drive signals is defined. The
corresponding R DEL resistor value to implement this delay is given by:
R DEL + T DEL1
0.91
10 11
W
s
(17)
or
R DEL + T DEL2
0.91
10 11
W
s
(18)
20
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| UCC2891DRG4 | 功能描述:电流型 PWM 控制器 Current Mode Active Clamp RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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| UCC2891PW | 功能描述:电流型 PWM 控制器 Current Mode Active Clamp RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| UCC2891PWG4 | 功能描述:电流型 PWM 控制器 Current Mode Active Clamp RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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