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| 型号： | UCC38051PE4 |
| 厂商： | Texas Instruments |
| 文件页数： | 14/32页 |
| 文件大小： | 0K |
| 描述： | IC PFC CTRLR TRANSITION 8DIP |
| 标准包装： | 50 |
| 模式： | 间歇（跃迁） |
| 频率 - 开关： | 200kHz |
| 电流 - 启动： | 75µA |
| 电源电压： | 12 V ~ 18 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 配用： | 296-19036-ND - EVAL MODULE FOR UCC28051 |
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UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F?SEPTEMBER 2002 ? REVISED MARCH 2009
APPLICATION INFORMATION
Sense Resistor Selection
The current sense resistor value must be chosen to limit the output power and it must also use the full dynamic
range of the multiplier during normal steady state operation. The value of R S1 is thus selected for maximum
power operation at low ac line voltage conditions. In order to use the full dynamic range, set the V SENSE
threshold as a function of the dynamic input range of V COMP and the peak of the minimum MULTIN voltage.
R S1 +
0.67
COMP (MAX) * COMP (MIN)
2 2
MULTIN (PEAK)@VAC(min) * 0.075
P IN(max)
V AC(min)
(12)
where:
D COMP (MAX) = 3.8 V
D COMP (MIN) = 2.5 V
D MULTIN (PEAK)@VAC(min) + 2
V AC(min)
R AC2
R AC2 ) R AC1
If the exact value R S1 is not available. R S2 and R S3 can be added for further scaling. The CS pin already has
an internal filter for noise due to switching transients. Additional filtering at switching transient frequencies can
be achieved by adding C S1 .
Output Voltage Sense Design
Select the divider ratio of R O1 and R O2 to set the VO_SNS voltage to 2.5 V at the desired output voltage. The
current through the divider should be at least 200 μ A.
Voltage Loop Design
How well the voltage control loop is designed directly impacts line current distortion. UCC38050 employs a
transconductance amplifier (g M amp) with gain scheduling for improved transient response (refer to Figure 14.
g M Amplifier Output Current vs. Current Sense Voltage ). Integral type control at low frequencies is preferred
here because the loop gain varies considerably with line conditions. The largest gain occurs at maximum line
voltage. If the power factor corrector load is dc-to-dc switching converter, the small signal model of the controller
and the power factor corrector, from COMP to PFC output voltage is given by:
^
V OUT (s)
^
V COMP (s)
+
V OUT(avg)
k 1
R S1
2
V AC
k CRM
C OUT
1
S
(13)
D V OUT = small signal variations in V OUT
D V COMP = small signal variations in V COMP
where:
^
^
D k 1 = multiplier gain = 0.65
D k CRM = peak to average factor = 2
14
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