参数资料
型号: UDA1334BTS/N2,112
厂商: NXP SEMICONDUCTORS
元件分类: DAC
英文描述: Low power audio DAC; Package: SOT369-1 (SSOP16); Container: Tube
中文描述: SERIAL INPUT LOADING, 24-BIT DAC, PDSO16
封装: 4.40 MM, PLASTIC, MO-152, SOT369-1, SSOP-16
文件页数: 21/22页
文件大小: 160K
代理商: UDA1334BTS/N2,112
2000 Jul 31
8
NXP Semiconductors
Product specification
Low power audio DAC
UDA1334BTS
8.4
Filter stream DAC
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at virtual
ground of the output operational amplifier. In this way very
high signal-to-noise performance and low clock jitter
sensitivity is achieved. No post-filter is needed due to the
inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
8.5
Power-on reset
The UDA1334BTS has an internal Power-on reset circuit
(see Fig.3) which resets the test control block.
The reset time (see Fig.4) is determined by an external
capacitor which is connected between pin Vref(DAC) and
ground. The reset time should be at least 1
μs for
Vref(DAC) < 1.25 V. When VDDA is switched off, the device
will be reset again for Vref(DAC) <0.75 V.
During the reset time the system clock should be running.
handbook, halfpage
VDDA
Vref(DAC)
3.0 V
13
12
MGL985
UDA1334BTS
C1
>
10
μF
RESET
CIRCUIT
50 k
Ω
50 k
Ω
Fig.3 Power-on reset circuit.
handbook, halfpage
3.0
VDDD
(V)
1.5
0
t
3.0
VDDA
(V)
1.5
0
t
3.0
Vref(DAC)
(V)
1.5
1.25
0.75
0
t
MGL984
>1 μs
Fig.4 Power-on reset timing.
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