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参数资料
| 型号： | UDA1380HN/N2,118 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 消费家电 |
| 英文描述： | Stereo audio coder-decoder for MD, CD and MP3; Package: SOT617-1 (HVQFN32); Container: Reel Pack, SMD, 13" |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封装： | 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32 |
| 文件页数： | 13/68页 |
| 文件大小： | 349K |
| 代理商： | UDA1380HN/N2,118 |
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2004 Apr 22
20
Philips Semiconductors
Product specication
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
8.13
Digital audio data input and output
The supported audio formats for the control modes are:
I2S-bus
MSB-justified
LSB-justified, 16 bits
LSB-justified, 18 bits
LSB-justified, 20 bits
LSB-justified, 24 bits (only for the output interface).
The bit clock BCK can be up to 128fs, or in other words the
BCK frequency is 128 times the WS frequency or less:
fBCK ≤ 128fWS.
Remark: The WS edge must coincide with the negative
edge of the BCK at all times, for proper operation of the
digital I/O data interface. Figure 13 shows the interface
signals.
8.13.1
DIGITAL AUDIO INPUT INTERFACE
The digital audio input interface is slave only, meaning the
system must provide the WSI and BCKI signals (next to
the DATAI signal).
Either the WSPLL locks onto the WSI signal and provides
the internal clocks for the interpolator and the FSDAC, or
a system clock must be applied which must be in
frequency lock to the digital data input interface signals.
8.13.2
DIGITAL AUDIO OUTPUT INTERFACE
The digital audio output interface can be either master or
slave. The data source for the data output can be selected
from either the decimator (ADC front-end) or the digital
mixer output.
Remark: The digital mixer output is only valid if both the
decimator and the interpolator run at the same clock:
In slave mode the signals on pins BCKO, WSO and
SYSCLK must be applied from the application (signals
must be in frequency lock) and the UDA1380 returns the
DATAO signal from the decimator. The applied signal
from pin BCKO can be for instance: 32fs, 48fs, 64fs,
96fs or 128fs
In master mode the SYSCLK signal must be applied
from the system, then the UDA1380 returns with the
BCKO, WSO and the DATAO signals. For the BCKO
clock, there are 2 general rules:
– When the SYSCLK is either 256fs or 512fs, the BCKO
frequency is 64fs
– When the SYSCLK is either 384fs or 768fs, the BCKO
signal is 48fs.
The slave and master modes can be selected by the
bit Serial Interface Mode (SIM) in the L3-bus or I2C-bus
interface.
9
L3-BUS INTERFACE DESCRIPTION
The UDA1380 has an L3-bus microcontroller
interface mode. Controllable system and digital sound
processing features are:
Software reset
System clock frequency (selection between 256fs,
384fs, 512fs and 768fs clock divider settings)
Clock mode setting, for instance, which block runs at
which clock, and clock enabling
Power control for the WSPLL
Data input and data output format control, for input and
output independently including data source selection for
the digital output interface
ADC features:
– Digital mute
– AGC enable and settings
– Polarity control
– Input line amplifier control (0 to 24 dB in steps of
3 dB)
– DC filtering control
– Digital gain control (+24 to
63 dB gain in steps of
0.5 dB) for left and right
– Power control
– VGA of the microphone input
– Selection of line or microphone input.
DAC and headphone driver features:
– Power control FSDAC and headphone driver
– Polarity control
– Mixing control (only available when both decimator
and interpolator run at the same speed). This
includes the mixer volumes, mute and mixer position
switch
– De-emphasis control
– Master volume and balance control
– Flat/minimum/maximum settings for bass boost and
treble
– Tone control: bass boost and treble
– Master mute control
– Headphone driver short-circuit protection status bits.
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