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参数资料
| 型号： | UPD62AMC-XXX-5A4-A |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | 0.300 INCH, PLASTIC, SSOP-20 |
| 文件页数： | 7/62页 |
| 文件大小： | 272K |
| 代理商： | UPD62AMC-XXX-5A4-A |
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15
PD62A
Data Sheet U14474EJ2V0DS00
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Name
KI/O7
KI/O6
KI/O5
KI/O4
KI/O3
KI/O2
KI/O1
KI/O0
b0 to b7: Read:
In input mode, the KI/O pin’s state is read.
In output mode, the KI/O pin’s output latch contents are read.
Write:
Data is written to the KI/O pin’s output latch regardless of input or output mode.
3.1 KI/O Port (P0)
The KI/O port is an 8-bit input/output port for key scan output.
Input/output mode is set by bit 1 of the P4 register.
If a read instruction is executed, the pin state can be read in input mode, whereas the output latch contents can
be read in output mode.
If the write instruction is executed, data can be written to the output latch regardless of input or output mode.
When reset, the port is placed in output mode; and the value of the output latch (P0) becomes 1111 1111B.
The KI/O port includes a pull-down resistor, allowing pull-down in input mode only.
Caution If a key is double-pressed, a high-level output and a low-level output may coincide at the
KI/O port. To avoid this, the low-level output current of the KI/O port is held low. Therefore, be
careful when using the KI/O port for purposes other than key scan output.
The KI/O port is so designed that, even when connected directly to VDD, within the normal supply
voltage range (VDD = 2.0 to 3.6 V), no problem may occur.
Table 3-2. KI/O Port (P0)
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