- 您现在的位置：买卖IC网 > PDF目录1971 > UPD70F3025AGC-33-8EU-A (Renesas Electronics America)MCU 32BIT 256K FLASH 100LQFP PDF资料下载
参数资料
| 型号： | UPD70F3025AGC-33-8EU-A |
| 厂商： | Renesas Electronics America |
| 文件页数： | 18/49页 |
| 文件大小： | 0K |
| 描述： | MCU 32BIT 256K FLASH 100LQFP |
| 标准包装： | 50 |
| 系列： | V853 |
| 核心处理器： | V850ES |
| 芯体尺寸： | 32-位 |
| 速度： | 33MHz |
| 连通性： | CSI，EBI/EMI，UART/USART |
| 外围设备： | PWM |
| 输入/输出数： | 67 |
| 程序存储器容量： | 256KB（256K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 数据转换器： | A/D 8x10b，D/A 2x8b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页当前第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页
2011 Microchip Technology Inc.
DS31037B-page 25
PIC24F16KL402 FAMILY
3.0
CPU
The PIC24F CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M instructions of user program
memory space. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double-word move
(MOV.D) instruction and the table instructions.
Overhead-free program loop constructs are supported
using the REPEAT instructions, which are interruptible
at any point.
PIC24F devices have sixteen, 16-bit working registers
in the programmer’s model. Each of the working
registers can act as a data, address or address offset
register. The 16th working register (W15) operates as a
Software Stack Pointer (SSP) for interrupts and calls.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K word boundary of either program memory or data
EEPROM memory, defined by the 8-bit Program Space
Visibility Page Address (PSVPAG) register. The pro-
gram to data space mapping feature lets any instruction
access program space as if it were data space.
The Instruction Set Architecture (ISA) has been
significantly enhanced beyond that of the PIC18, but
maintains
an
acceptable
level
of
backward
compatibility. All PIC18 instructions and addressing
modes are supported, either directly, or through simple
macros. Many of the ISA enhancements have been
driven by compiler efficiency needs.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct and three groups of addressing
modes. All modes support Register Direct and various
Register Indirect modes. Each group offers up to seven
addressing modes. Instructions are associated with
predefined addressing modes depending upon their
functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working
register (data) read, a data memory write and a
program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing trinary operations (i.e., A + B = C)
to be executed in a single cycle.
A high-speed, 17-bit by 17-bit multiplier has been
included to significantly enhance the core arithmetic
capability and throughput. The multiplier supports
Signed, Unsigned and Mixed mode, 16-bit by 16-bit or
8-bit by 8-bit integer multiplication. All multiply
instructions execute in a single cycle.
The 16-bit ALU has been enhanced with integer divide
assist hardware that supports an iterative non-restoring
divide algorithm. It operates in conjunction with the
REPEAT
instruction looping mechanism and a selection
of iterative divide instructions to support 32-bit (or
16-bit), divided by a 16-bit integer signed and unsigned
division. All divide operations require 19 cycles to
complete, but are interruptible at any cycle boundary.
The PIC24F has a vectored exception scheme, with up
to eight sources of non-maskable traps and up to
118 interrupt sources. Each interrupt source can be
assigned to one of seven priority levels.
A block diagram of the CPU is illustrated in Figure 3-1.
3.1
Programmer’s Model
Figure 3-2 displays the programmer’s model for the
PIC24F. All registers in the programmer’s model are
memory mapped and can be manipulated directly by
instructions.
Table 3-1 provides a description of each register. All
registers associated with the programmer’s model are
memory mapped.
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on the
CPU, refer to the “PIC24F Family
Reference Manual”
, Section 2. “CPU”
(DS39703).
相关PDF资料 |
PDF描述 |
|---|---|
| UPD70F3201YGC-YEU-A | MCU 32BIT I2C 100TQFP |
| UPD70F3452GC-UBT-A | MCU 32BIT 256KB FLASH 80LQFP |
| UPD70F3714GC-8BS-A | MCU 32BIT V850ES/LX2 64-LQFP |
| UPD70F3757GJ-GAE-AX | MCU 32BIT V850ES/HX3 144-LQFP |
| UPD720101GJ-UEN-A | HOST CTLR USB 2.0 144-LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| UPD70F3030B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:V850 Series Pamphlet | Pamphlet[02/2002] |
| UPD70F3030BY | 制造商:未知厂家 制造商全称:未知厂家 功能描述:V850/SB1(TM).V850/SB2(TM) for Hardware | UM Including Electrical Characteristics[02/2003] |
| UPD70F3032A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:The RISC power shapes your imagination Pamphlet | Pamphlet[05/2002] |
| UPD70F3032AY | 制造商:未知厂家 制造商全称:未知厂家 功能描述:V850 Family(TM) for Architecture | User＇s Manual[03/2001] |
| UPD70F3032B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:V850 Series Pamphlet | Pamphlet[02/2002] |
发布紧急采购，3分钟左右您将得到回复。