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参数资料
| 型号： | UPD780021AYCW-XXX |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8.38 MHz, MICROCONTROLLER, PDIP64 |
| 封装： | 0.750 INCH, PLASTIC, SDIP-64 |
| 文件页数： | 52/96页 |
| 文件大小： | 723K |
| 代理商： | UPD780021AYCW-XXX |
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56
PD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Data Sheet U14042EJ4V0DS
Capacitance (TA = 25
°C, VDD = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input
CIN
f = 1 MHz
15
pF
capacitance
Unmeasured pins returned to 0 V.
I/O
CIO
f = 1 MHz
P00 to P03, P20 to P25,
15
pF
capacitance
Unmeasured pins
P34 to P36, P40 to P47,
returned to 0 V.
P50 to P57, P64 to P67,
P70 to P75
P30 to P33
20
pF
Remark
Unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins.
Resonator
Recommended
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
Circuit
Ceramic
Oscillation
4.0 V
≤ VDD ≤ 5.5 V
1.0
8.38
MHz
resonator
frequency (fX)Note 1
1.8 V
≤ VDD < 4.0 V
1.0
5.0
Oscillation
After VDD reaches
4
ms
stabilization timeNote 2
oscillation voltage range
MIN.
Crystal
Oscillation
4.0 V
≤ VDD ≤ 5.5 V
1.0
8.38
MHz
resonator
frequency (fX)Note 1
1.8 V
≤ VDD < 4.0 V
1.0
5.0
Oscillation
4.0 V
≤ VDD ≤ 5.5 V
10
ms
stabilization timeNote 2
1.8 V
≤ VDD < 4.0 V
30
External
X1 input
4.0 V
≤ VDD ≤ 5.5 V
1.0
8.38
MHz
clock
frequency (fX)Note 1
1.8 V
≤ VDD < 4.0 V
1.0
5.0
X1 input
4.0 V
≤ VDD ≤ 5.5 V
50
500
ns
high-/low-level width
1.8 V
≤ VDD < 4.0 V
85
500
(tXH, tXL)
Main System Clock Oscillator Characteristics (TA = –40 to +85
°C, VDD = 1.8 to 5.5 V)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions
1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS1.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
C2
C1
X1
X2
IC
C2
C1
X1
X2
IC
X2
X1
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