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CHAPTER 18
I2C BUS MODE (
PD784225Y SUBSERIES ONLY)
User’s Manual U12697EJ4V1UD
Figure 18-3. Format of I2C Bus Control Register 0 (IICC0) (4/4)
SPT0
Stop condition trigger
0
The stop condition is not generated.
1
The stop condition is generated (ends the transfer as the master).
After the SDA0 line goes low, the SCL0 line goes high, or wait until SCL0 goes high. Then, the
standard time is guaranteed; the SDA0 line is changed from low to high; and the stop condition is
generated.
Cautions on set timing
Master reception:
Setting is prohibited during transfer.
SPT0 can be set only during the wait period after ACK0=0 is set and the fact that
reception is completed is passed to the slave.
Master transmission:
During the ACK0 acknowledge period, the start condition may not be normally
generated. Set SPT0 during the wait period.
Setting synchronized to STT0 is prohibited.
Resetting between setting SPT0 and the generation of the clear condition is prohibited.
Set SPT0 only by the masterNote.
When WTIM0 = 0 is set, be aware that if SPT0 is set during the wait period after the eighth clock is output,
the stop condition is generated during the high level of the ninth clock after the wait is released.
When the ninth clock must be output, set WTIM0 = 0
→ 1 during the wait period after the eighth clock is
output, and set SPT0 during the wait period after the ninth clock is output.
Clear condition (SPT0 = 0)
Set condition (SPT0 = 1)
Cleared by an instruction
Set by an instruction
IICE0 = 0
LREL0 = 0
When arbitration failed
Automatically clear after the stop condition is detected
When RESET is input
Note Set SPT0 only by the master. However, SPT0 must be set once and the stop condition generated to operate
the master by the time the first stop condition is detected after operation is enabled. For details, refer to
18.5.15 Additional warnings.
Cautions 1. When bit 3 (TRC0) = 1 in I2C bus status register 0 (IICS0), after WREL0 is set at the ninth clock
and the wait is released, TRC0 is cleared, and the SDA0 line becomes high impedance.
2. SPT0 and STT0 are 0 when read after data has been set.
Remark
STD0:
Bit 1 in I2C bus status register 0 (IICS0)
ACKD0: Bit 2 in I2C bus status register 0 (IICS0)
TRC0:
Bit 3 in I2C bus status register 0 (IICS0)
COI0:
Bit 4 in I2C bus status register 0 (IICS0)
EXC0:
Bit 5 in I2C bus status register 0 (IICS0)
MSTS0: Bit 7 in I2C bus status register 0 (IICS0)