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CHAPTER 22
INTERRUPT FUNCTIONS
User’s Manual U12697EJ4V1UD
22.7.1 Vectored interrupt
When a vectored interrupt maskable interrupt request is acknowledged, the program status word (PSW) and
program counter (PC) are saved in that order to the stack, the IE flag is cleared (0) (the interrupt disabled status is
set), and the in-service priority register (ISPR) bit corresponding to the priority of the acknowledged interrupt is set
(1). Also, data in the vector table predetermined for each interrupt request is loaded into the PC, and a branch is
performed. The return from a vectored interrupt is performed by means of the RETI instruction.
Caution When a maskable interrupt is acknowledged by vectored interrupt, the RETI instruction must be
used to return from the interrupt. Subsequent interrupt acknowledgment will not be performed
normally if a different instruction is used.
22.7.2
Context switching
Initiation of the context switching function is enabled by setting (1) the context switching enable flag of the interrupt
control register.
When an interrupt request for which the context switching function is enabled is acknowledged, the register bank
specified by the lowest 3 bits of the lower address (even address) of the corresponding vector table address is selected.
The vector address stored beforehand in the selected register bank is transferred to the program counter (PC),
and at the same time the contents of the PC and program status word (PSW) up to that time are saved in the register
bank and branching is performed to the interrupt service program.
Figure 22-12. Context Switching Operation by Generation of an Interrupt Request
Register bank
(0 to 7)
A
B
R5
R7
X
C
R4
R6
D
H
VP
UP
E
L
V
U
T
W
Register bank n (n = 0 to 7)
7 Transfer
6 Exchange
4
2 Save
(Temporary
register
bits 8 to 11)
5 Save
1 Save
PC15-0
PC19-16
0000B
Temporary register
PSW
n
3 Register bank switching
(RSB0-RSB2
← n)
Vector table
RSS
← 0
(
IE
← 0
)