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APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
850
(5/34)
Chapter
Cl
assi
fi
cati
on
Function
Details of
Function
Cautions
Page
CSC: Clock
operation status
control register
The setting of the flags of the register to stop clock oscillation (invalidate the external
clock input) and the condition before clock oscillation is to be stopped are as follows.
(See Table 5-2.)
p.157
After the above time has elapsed, the bits are set to 1 in order from MOST8 and
remain 1.
p.158
Soft
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. In the following cases, set the oscillation stabilization time of OSTS to
the value greater than or equal to the count value which is to be checked by the
OSTC register after the oscillation starts.
If the X1 clock starts oscillation while the internal high-speed oscillation clock or
subsystem clock is being used as the CPU clock. If the STOP mode is entered and
then released while the internal
If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
p.158
Hard
OSTC:
Oscillation
stabilization time
counter status
register
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
p.158
To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS
register before executing the STOP instruction.
p.160
Setting the oscillation stabilization time to 20
μs or less is prohibited.
p.160
To change the setting of the OSTS register, be sure to confirm that the counting
operation of the OSTC register has been completed.
p.160
Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
p.160
Soft
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. In the following cases, set the oscillation stabilization time of OSTS to
the value greater than or equal to the count value which is to be checked by the
OSTC register.
If the X1 clock starts oscillation while the internal high-speed oscillation clock or
subsystem clock is being used as the CPU clock.
If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
p.160
Hard
OSTS:
Oscillation
stabilization time
select register
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
p.160
Be sure to set bit 3 to 1.
p.162
Soft
The clock set by CSS, MCM0, and MDIV2 to MDIV0 is supplied to the CPU and
peripheral hardware. If the CPU clock is changed, therefore, the clock supplied to
peripheral hardware (except the real-time counter, clock output/buzzer output, and
watchdog timer) is also changed at the same time.
Consequently, stop each
peripheral function when changing the CPU/peripheral operating hardware clock.
p.162
Chapter
5
Hard
Clock
generator
CKC: System
clock control
register
If the peripheral hardware clock is used as the subsystem clock, the operations of the
A/D converter and IIC0 are not guaranteed. For the operating characteristics of the
peripheral hardware, refer to the chapters describing the various peripheral hardware
as
well
as
CHAPTER
28
ELECTRICAL
SPECIFICATIONS
(STANDARD
PRODUCTS) and CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS).
p.162