APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
852
(7/34)
Chapter
Cl
assi
fi
cati
on
Function
Details of
Function
Cautions
Page
A voltage oscillation stabilization time is required after the supply voltage reaches
1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.07 V (TYP.) within
the power supply oscillation stabilization time, the power supply oscillation
stabilization time is automatically generated before reset processing.
p.175
Hard
Clock
generator
operation
when
power
supply
voltage is
turned on
When LVI
default start
function enabled
is set (option
byte: LVIOFF =
0)
It is not necessary to wait for the oscillation stabilization time when an external clock
input from the EXCLK pin is used.
p.175
X1/P121,
X2/EXCLK/P122
The X1/P121 and X2/EXCLK/P122 pins are in the input port mode after a reset
release.
p.176
The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
Therefore, it is necessary to also set the value of the
OSCSELS bit at the same time. For OSCSELS bit, see 5.6.3 Example of controlling
subsystem clock.
p.176
X1 clock
Set the X1 clock after the supply voltage has reached the operable voltage of the
clock to be used (see CHAPTER 28 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) and CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS)).
p.176
The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
Therefore, it is necessary to also set the value of the
OSCSELS bits at the same time.
For OSCSELS bits, see 5.6.3 Example of
controlling subsystem clock.
p.177
External main
system clock
Set the external main system clock after the supply voltage has reached the operable
voltage of the clock to be used (see CHAPTER 28 ELECTRICAL SPECIFICATIONS
(STANDARD PRODUCTS) and CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A)
GRADE PRODUCTS)).
p.177
Be sure to clear bit 1 of the PER0 register to 0.
p.178
Controlling
high-speed
system
clock
High-speed
system clock
Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition,
stop peripheral hardware that is operating on the high-speed system clock.
p.179
If switching the CPU/peripheral hardware clock from the high-speed system clock to
the internal high-speed oscillation clock after restarting the internal high-speed
oscillation clock, do so after 10
μs or more have elapsed.
If the switching is made immediately after the internal high-speed oscillation clock is
restarted, the accuracy of the internal high-speed oscillation cannot be guaranteed
for 10
μs.
p.180
Controlling
internal
high-speed
oscillation
clock
Internal high-
speed oscillation
clock
Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP to 1. In addition,
stop peripheral hardware that is operating on the internal high-speed oscillation clock.
p.181
Soft
XT1/P123,
XT2/P124
The XT1/P123 and XT2/P124 pins are in the input port mode after a reset release.
p.181
Chapter
5
Hard
Subsystem
clock
control
Subsystem clock When the subsystem clock is used as the CPU clock, the subsystem clock is also
supplied
to
the
peripheral
hardware
(except
the
real-time
counter,
clock
output/buzzer output, and watchdog timer). At this time, the operations of the A/D
converter and IIC0 are not guaranteed.
For the operating characteristics of the
peripheral hardware, refer to the chapters describing the various peripheral hardware
as
well
as
CHAPTER
28
ELECTRICAL
SPECIFICATIONS
(STANDARD
PRODUCTS) and CHAPTER 29 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS).
pp.181,
182