APPENDIX B LIST OF CAUTIONS
User’s Manual U18432EJ5V0UD
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Chapter
Cl
assi
fi
cati
on
Function
Details of
Function
Cautions
Page
When STCEN =
0
Immediately after I
2C operation is enabled (IICE0 = 1), the bus communication status
(IICBSY (bit 6 of IICF0) = 1) is recognized regardless of the actual bus status. When
changing from a mode in which no stop condition has been detected to a master
device communication mode, first generate a stop condition to release the bus, then
perform master device communication.
When using multiple masters, it is not possible to perform master device
communication when the bus has not been released (when a stop condition has not
been detected).
Use the following sequence for generating a stop condition.
<1> Set IIC clock select register 0 (IICCL0).
<2> Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1.
<3> Set bit 0 (SPT0) of IICC0 to 1.
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When STCEN =
1
Immediately after I
2C operation is enabled (IICE0 = 1), the bus released status
(IICBSY = 0) is recognized regardless of the actual bus status. To generate the first
start condition (STT0 (bit 1 of IIC control register 0 (IICC0)) = 1), it is necessary to
confirm that the bus has been released, so as to not disturb other communications.
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If other I
2C
communications
are already in
progress
If I
2C operation is enabled and the device participates in communication already in
progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I
2C
recognizes that the SDA0 pin has gone low (detects a start condition). If the value on
the bus at this time can be recognized as an extension code, ACK is returned, but
this interferes with other I
2C communications. To avoid this, start I2C in the following
sequence.
<1> Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request
signal (INTIIC0) when the stop condition is detected.
<2> Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I
2C.
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after
setting IICE0 to 1), to forcibly disable detection.
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Setting transfer
clock frequency
Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, and 0
of IICL0), and CLX0 (bit 0 of IICX0) before enabling the operation (IICE0 = 1). To
change the transfer clock frequency, clear IICE0 to 0 once.
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STT0, SPT0:
Bits 1, 0 of IIC
control register 0
(IICC0)
Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and before
they are cleared to 0 is prohibited.
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Chapter
1
4
Soft
Serial
interface
IIC0
Reserving
transmission
When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt
request is generated when the stop condition is detected. Transfer is started when
communication data is written to IIC0 after the interrupt request is generated. Unless
the interrupt is generated when the stop condition is detected, the device stops in the
wait state because the interrupt request is not generated when communication is
started. However, it is not necessary to set SPIE0 to 1 when MSTS0 (bit 7 of IICS0)
is detected by software.
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Be sure to clear bits 15 to 10 to “0”.
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Chapter
1
6
Soft
DMA
controller
DBCn: DMA
byte count
register n
If the general-purpose register is specified or the internal RAM space is exceeded as
a result of continuous transfer, the general-purpose register or SFR space are written
or read, resulting in loss of data in these spaces. Be sure to set the number of times
of transfer that is within the internal RAM space.
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