APPENDIX B LIST OF CAUTIONS
User’s Manual U18432EJ5V0UD
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Chapter
Cl
assi
fi
cati
on
Function
Details of
Function
Cautions
Page
Chapter
2
1
Soft
Power-on-
clear
circuit
Cautions for
power-on-clear
circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the
vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and
released from the reset status. In this case, the time from release of reset to the start
of the operation of the microcontroller can be arbitrarily set by taking the following
action.
p.708
Soft
To stop LVI, follow either of the procedures below.
When using 8-bit memory manipulation instruction: Write 00H to LVIM.
When using 1-bit memory manipulation instruction: Clear LVION to 0.
p.713
Hard
Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
p.713
LVIM: Low-
voltage detection
register
When LVI is used in interrupt mode (LVIMD = 0) and LVISEL is set to 0, an interrupt
request signal (INTLVI) that disables LVI operation (clears LVION) when the supply
voltage (VDD) is less than or equal to the detection voltage (VLVI) (if LVISEL = 1, input
voltage of external input pin (EXLVI) is less than or equal to the detection voltage
(VEXLVI)) is generated and LVIIF may be set to 1.
p.713
Be sure to clear bits 4 to 7 to “0”.
p.714
Change the LVIS value with either of the following methods.
When changing the value after stopping LVI
<1> Stop LVI (LVION = 0).
<2> Change the LVIS register.
<3> Set to the mode used as an interrupt (LVIMD = 0).
<4> Mask LVI interrupts (LVIMK = 1).
<5> Enable LVI operation (LVION = 1).
<6> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
because an LVIIF flag may be set when LVI operation is enabled.
When changing the value after setting to the mode used as an interrupt (LVIMD =
0)
<1> Mask LVI interrupts (LVIMK = 1).
<2> Set to the mode used as an interrupt (LVIMD = 0).
<3> Change the LVIS register.
<4> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
because an LVIIF flag may be set when the LVIS register is changed.
p.715
LVIS: Low-
voltage detection
level select
register
When an input voltage from the external input pin (EXLVI) is detected, the detection
voltage (VEXLVI) is fixed. Therefore, setting of LVIS is not necessary.
p.715
<1> must always be executed.
When LVIMK = 0, an interrupt may occur
immediately after the processing in <4>.
p.717
Used as reset
(when detecting
level of supply
voltage (VDD))
(LVIOFF = 1)
If supply voltage (VDD)
≥ detection voltage (VLVI) when LVIMD is set to 1, an internal
reset signal is not generated.
p.717
Chapter
2
Soft
Low-
voltage
detector
Used as reset
(when detecting
level of supply
voltage (VDD))
(LVIOFF = 0)
Even when the LVI default start function is used, if it is set to LVI operation
prohibition by the software, it operates as follows:
Does not perform low-voltage detection during LVION = 0.
If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
μs
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
p.719