CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15400EJ4V0UD
64
Table 3-4. Special Function Registers (2/3)
Bit Unit for Manipulation
Address
Special Function Register (SFR) Name
Symbol
R/W
1 Bit
8 Bits
16 Bits
After
Reset
FF48H
16-bit timer mode control register 20
TMC20
√
FF4AH
Watch timer mode control register
WTM
√
FF4BH
Watch timer interrupt time selection register
WTIM
R/W
√
00H
FF4CH
8-bit H width compare register 60
CRH60
W
√
Undefined
FF4DH
8-bit timer mode control register 50
TMC50
√
FF4EH
8-bit timer mode control register 60
TMC60
√
FF4FH
Carrier generator output control register 60
TCA60
R/W
√
FF57H
Port function register 7
Note
PF7
√
FF58H
Port function register 8
Note
PF8
W
√
FF60H
Remote controller receive control register
RMCN
R/W
√
FF61H
Remote controller receive data register
RMDR
√
FF62H
Remote controller shift register receive counter
register
RMSCR
√
FF63H
Remote controller receive shift register
RMSR
R
√
FF64H
Remote controller receive GPLS compare register
RMGPLS
√
FF65H
Remote controller receive GPLL compare register
RMGPLL
√
FF66H
Remote controller receive GPHS compare register
RMGPHS
√
FF67H
Remote controller receive GPHL compare register
RMGPHL
√
FF68H
Remote controller receive DLS compare register
RMDLS
√
FF69H
Remote controller receive DLL compare register
RMDLL
√
FF6AH
Remote controller receive DH0S compare register
RMDH0S
√
FF6BH
Remote controller receive DH0L compare register
RMDH0L
√
FF6CH
Remote controller receive DH1S compare register
RMDH1S
√
FF6DH
Remote controller receive DH1L compare register
RMDH1L
√
FF6EH
Remote controller receive end width selection
register
RMER
√
FF70H
Asynchronous serial interface mode register 20
ASIM20
R/W
√
FF71H
Asynchronous serial interface status register 20
ASIS20
R
√
FF72H
Serial operation mode register 20
CSIM20
√
FF73H
Baud rate generator control register 20
BRGC20
R/W
√
00H
Transmit shift register 20
TXS20
W
√
FFH
FF74H
Receive buffer register 20
RXB20
SIO20
R
√
Undefined
FF78H
Serial operation mode register 1A0
CSIM1A0
√
FF79H
Automatic data transmit/receive control register 0
ADTC0
√
00H
FF7AH
Automatic data transmit/receive address pointer 0
ADTP0
R/W
√
Undefined
FF7BH
Automatic data transmit/receive interval specification
register 0
ADTI0
√
00H
Note These registers function only in the
μPD78F9478 and 78F9479; however, writing to these registers in the
μPD789477, 789478, and 789479 will not affect the operation.