参数资料
型号: uPSD3212C
厂商: 意法半导体
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(带8032微控制器内核和16Kbit SRAM的FLASH可编程系统器件)
中文描述: 闪存可编程系统设备与8032微控制器内核和16Kbit的SRAM(带8032微控制器内核和16Kbit SRAM的的闪存可编程系统器件)
文件页数: 67/151页
文件大小: 1194K
代理商: UPSD3212C
67/151
uPSD3212C, uPSD3212CV
ANALOG-TO-DIGITAL CONVERTOR (ADC)
The analog to digital (A/D) converter allows con-
version of an analog input to a corresponding 8-bit
digital value. The A/D module has four analog in-
puts, which are multiplexed into one sample and
hold. The output of the sample and hold is the in-
put into the converter, which generates the result
via successive approximation. The analog supply
voltage is connected to AVREF of ladder resis-
tance of A/D module.
The A/D module has two registers which are the
control register ACON and A/D result register
ADAT. The register ACON, shown in Table 46 and
Table 47, page 68, controls the operation of the A/
D converter module. To use analog inputs, I/O is
selected by P1SFS register. Also an 8-bit prescal-
er ASCL divides the main system clock input down
to approximately 6MHz clock that is required for
the ADC logic. Appropriate values need to be load-
ed into the prescaler based upon the main MCU
clock frequency prior to use.
The processing of conversion starts when the
Start Bit ADST is set to '1.' After one cycle, it is
cleared by hardware. The register ADAT contains
the results of the A/D conversion. When conver-
sion is completed, the result is loaded into the
ADAT the A/D Conversion Status Bit ADSF is set
to '1.'
The block diagram of the A/D module is shown in
Figure 34. The A/D Status Bit ADSF is set auto-
matically when A/D conversion is completed,
cleared when A/D conversion is in process.
The ASCL should be loaded with a value that re-
sults in a clock rate of approximately 6MHz for the
ADC using the following formula (see Table 48,
page 68):
ADC clock input = (f
OSC
/ 2) / (Prescaler register
value +1)
Where f
OSC
is the MCU clock input frequency
The conversion time for the ADC can be calculat-
ed as follows:
ADC Conversion Time = 8 clock * 8bits * (ADC
Clock) ~= 10.67usec (at 6MHz)
ADC Interrupt
The ADSF Bit in the ACON register is set to '1'
when the A/D conversion is complete. The status
bit can be driven by the MCU, or it can be config-
ured to generate a falling edge interrupt when the
conversion is complete.
The ADSF Interrupt is enabled by setting the ADS-
FINT Bit in the PCON register. Once the bit is set,
the external INT1 Interrupt is disabled and the
ADSF Interrupt takes over as INT1. INT1 must be
configured as if it is an edge interrupt input. The
INP1 pin (p3.3) is available for general I/O func-
tions, or Timer1 gate control.
Figure 34. A/D Block Diagram
AI06627
Input
MUX
ACH0
ACH1
ACH2
ACH3
ACON
INTERNAL BUS
ADAT
AVREF
Ladder
Resistor
D
ecode
S/H
Successive
Approximation
Circuit
Conversion
Complete
Interrupt
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UPSD3212C-24U1T 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM
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