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参数资料
型号： UPSD3234AV-40U6T
厂商： 意法半导体
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
中文描述： 闪存可编程系统设备与8032微控制器核心和64Kbit SRAM的
文件页数： 57/176页
文件大小： 1081K
代理商： UPSD3234AV-40U6T
57/176
μ
PSD323X
Table 40. Timer/Counter 2 Control Register (T2CON)
Table 41. Description of the T2CON Bits
Note: 1. The RCLK1 and TCLK1 Bits in the PCON Register control UART 2, and have the same function as RCLK and TCLK.
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Bit
Symbol
Function
7
TF2
Timer 2 overflow flag. Set by a Timer 2 overflow, and must be cleared by software. TF2
will not be set when either (RCLK, RCLK1)=1 or (TCLK, TCLK)=1
6
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2=1. When Timer 2 interrupt is enabled, EXF2=1 will
cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by
software
5
RCLK
1
Receive clock flag (UART 1). When set, causes the serial port to use Timer 2 overflow
pulses for its receive clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be
used for the receive clock
4
TCLK
1
Transmit clock flag (UART 1). When set, causes the serial port to use Timer 2 overflow
pulses for its transmit clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be
used for the transmit clock
3
EXEN2
Timer 2external enable flag. When set, allows a capture orreload to occur as a result of
a negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2=0 causes Time 2 to ignore events at T2EX
2
TR2
Start/stop control for Timer 2. A logic 1 starts the timer
1
C/T2
Timer or Counter select for Timer 2. Cleared for timer operation (input from internal
system clock, t
CPU
); set for external event counter operation (negative edge triggered)
0
CP/RL2
Capture/reload flag. When set, capture will occur on negative transition of T2EX if
EXEN2=1. When cleared, auto-reload will occur either with TImer 2 overflows, or
negative transitions of T2EX when EXEN2=1. When either (RCLK, RCLK1)=1 or (TCLK,
TCLK)=1, this bit is ignored, and timer is forced to auto-reload on Timer 2 overflow
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