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参数资料
| 型号： | UT6264C(E) |
| 英文描述： | 4 Mb (512K x 8, 256K x 16) Boot Sector, Flash Memory |
| 中文描述： | 异步静态RAM高速 |
| 文件页数： | 12/13页 |
| 文件大小： | 132K |
| 代理商： | UT6264C(E) |
UTRON
UT6264C
Rev. 1.4
8K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
Notes :
1. WE , CE must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE , high CE2, low WE .
3. During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on
the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CE low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a high
impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
DATA RETENTION CHARACTERISTICS (TA = 0J to 70J/ -20J to 85J (E))
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Vcc for Data Retention
VDR
CE VCC-0.2V or CE2 ≤ 0.2V
2.0
-
5.5
V
-L
-
1
50
A
Data Retention Current
IDR
Vcc=2V
CE VCC-0.2V or CE2 ≤ 0.2V
-LL
-
0.5
10
A
Chip Disable to Data
Retention Time
tCDR
See Data RetentionWaveforms
(below)
0
-
ns
Recovery Time
tR
tRC*
-
ns
tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (
CE controlled)
VDR
2V
CE
VCC-0.2V
Vcc(min.)
VIH
VCC
tR
tCDR
CE
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR
2V
VCC(min.)
VCC
tR
tCDR
CE2
0.2V
VIL
CE2
VCC(min.)
VIL
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| UT6264CPC-35 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8K X 8 BIT LOW POWER CMOS SRAM |
| UT6264CPC-35L | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8K X 8 BIT LOW POWER CMOS SRAM |
| UT6264CPC-35LL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8K X 8 BIT LOW POWER CMOS SRAM |
| UT6264CPC-70 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8K X 8 BIT LOW POWER CMOS SRAM |
| UT6264CPC-70L | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8K X 8 BIT LOW POWER CMOS SRAM |
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