参数资料
型号: UT6264C(E)
英文描述: 4 Mb (512K x 8, 256K x 16) Boot Sector, Flash Memory
中文描述: 异步静态RAM高速
文件页数: 9/13页
文件大小: 132K
代理商: UT6264C(E)
UTRON
UT6264C
Rev. 1.4
8K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC.
P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
CAPACITANCE (TA=25J , f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX
UNIT
Input Capacitance
CIN
-
8
pF
Input/Output Capacitance
CI/O
-
10
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Times
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
CL = 100pF, IOH/IOL = -1mA/4mA
AC ELECTRICAL CHARACTERISTICS (VCC = 4.5V~5.5V, TA = 0J to 70J/ -20J to 85J (E))
(1) READ CYCLE
UT6264C-35
UT6264C-70
PARAMETER
SYMBOL
MIN.
MAX.
MIN.
MAX.
UNIT
Read Cycle Time
tRC
35
-
70
-
ns
Address Access Time
tAA
-
35
-
70
ns
Chip Enable Access Time
tACE
-
35
-
70
ns
Output Enable Access Time
tOE
-
25
-
35
ns
Chip Enable to Output in Low-Z
tCLZ*
10
-
10
-
ns
Output Enable to Output in Low-Z
tOLZ*
5
-
5
-
ns
Chip Disable to Output in High-Z
tCHZ*
-
25
-
35
ns
Output Disable to Output in High-Z
tOHZ*
-
25
-
35
ns
Output Hold from Address Change
tOH
5
-
5
-
ns
(2) WRITE CYCLE
UT6264C-35
UT6264C-70
PARAMETER
SYMBOL
MIN.
MAX.
MIN.
MAX.
UNIT
Write Cycle Time
tWC
35
-
70
-
ns
Address Valid to End of Write
tAW
30
-
60
-
ns
Chip Enable to End of Write
tCW
30
-
60
-
ns
Address Set-up Time
tAS
0
-
0
-
ns
Write Pulse Width
tWP
25
-
50
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Data to Write Time Overlap
tDW
20
-
30
-
ns
Data Hold from End of Write-Time
tDH
0
-
0
-
ns
Output Active from End of Write
tOW*
5
-
5
-
ns
Write to Output in High-Z
tWHZ*
-
15
-
25
ns
*These parameters are guaranteed by device characterization, but not production tested.
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