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| 型号： | V21B |
| 厂商： | Mide Technology Corporation |
| 文件页数： | 20/24页 |
| 文件大小： | 0K |
| 描述： | PIEZOELECTRIC ENERGY HARVESTER |
| 产品培训模块： | Volture EHE004 Piezoelectric Energy Harvesting Conditioning Circuit |
| 产品目录绘图： | Volture Series Sensors Side |
| 标准包装： | 1 |
| 系列： | Volture™ |
| 传感器类型： | 加速 |
| 传感范围： | 80Hz ~ 205Hz |
| 输出类型： | 模拟 |
| 工作温度： | -40°C ~ 90°C |
| 特点： | 压电式振动能量收集，全密闭式密封 |
| 封装/外壳： | 悬臂压电薄膜（晶片） |
| 安装类型： | 通孔 |
| 端子： | PC 引脚 |
| 相关产品： | VR001-ND - VIBRATION DATA LOGGER |
APPLICATIONS INFORMATION - LOAD ISOLATION EXAMPLE
Considerations for Conversion Efficiency
Converter efficiency is defined as the output power
divided by the input power times 100%.
The losses from the circuit’s front-end components
(leakage across the storage capacitor, comparator, and
R1-R3) will be small (uA) and largely proportional to
the C1 voltage setpoint. Minimizing losses here is
straightforward by appropriate component selection of
C1 and suitably large values of R1 – R3. These small
losses will occur for the entire time that voltage is
present on C1.
The remaining controllable losses will occur in the
step-down converter section and, apart from the
LT1474’s shutdown current, occur only during the ON-
time of the output. The main losses will come from
three sources: V IN current, I 2 R losses, and catch diode
losses.
V IN
The V IN current of the LT1474 is due to two
components: the DC bias current and the gate charge
current of its internal P-channel switch. Both are
proportional to V IN ; however, at load currents > 1mA,
the DC bias current (from 9uA at no load to 100uA in
continuous mode) is negligible compared to the gate
charge losses. Each time the gate is switched on and
off, a packet of charge dQ moves from V IN to ground.
In continuous mode, I GATE = fQp where Qp is the gate
charge of the internal switch and f is the switching
frequency. Since V IN is pre-set according to piezo
efficiency considerations, the best way to minimize this
loss is to keep the output duty cycle low.
Resistive (I 2 R) Losses
The resistances in the current path (The ON-resistance
of the internal switch, current sense resistor, and
inductor) contribute resistive losses. At low values of
V IN , switch losses will dominate, and can be minimized
by using a suitably large inductor and low I PEAK . At
higher supply voltages, these losses are proportional to
load.
Catch Diode Losses
The catch diode, D7, introduces a loss (V*I) as it
conducts during the switch off-time, proportional to its
forward voltage, and more pronounced at high supply
voltage where the switch on-time is shorter. Again, V IN
is fixed for piezo efficiency reasons, so this loss is best
minimized by minimizing the diode V f and converter
duty cycle. By lowering the duty cycle, a reduction in V f
of the catch diode will improve efficiency even though
low-V f diodes tend to have much higher reverse
leakage currents, which will produce loss during the
switch ON-time. In any event, the catch diode must be
sized to safely handle I PEAK at nearly 100% duty cycle
(worst-case condition; output shorted).
The selection of 100uH inductor should be considered
a minimum, for use in conjunction with high I PEAK
values. Particularly in applications where space is not
constrained or I PEAK must be reduced, inductors as
large as 1000uH may be required for maximum
efficiency. The ideal range of inductor size at a given
I MAX is a trade-off between the increased resistance of
higher-value inductors and the increased switching
rates required for lower-value inductors.
At light loads, the output duty cycle will rise and losses
in the conversion stage (leakage, switching and catch
diode losses) will accrue. This may or may not be a
problem; it could simply mean that more power is
available than the load can use.
REVISION N0. 002
REVISION DATE: 01-23-2013
20
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