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参数资料
| 型号： | V54C3128164VBLJ-7IPC |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM, PBGA60 |
| 封装： | GREEN, MO-210, FBGA-60 |
| 文件页数： | 9/56页 |
| 文件大小： | 725K |
| 代理商： | V54C3128164VBLJ-7IPC |
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17
V54C3128(16/80/40)4VB*I Rev. 1.5 June 2008
ProMOS TECHNOLOGIES
V54C3128(16/80/40)4VB*I
Recommended Operation and Characteristics for LV-TTL
TA = -40 to +85 °C; VSS = 0 V; VCC,VCCQ = (+3.0V~3.3 V) ± 0.3 V
Note:
1.
All voltages are referenced to VSS.
2.
VIH may overshoot to VCC + 2.0 V for pulse width of < 4ns with 3.3V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with
3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
Operating Currents (TA = -40 to +85°C, VCC = (+3.0V~3.3V) ± 0.3V)
(Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Limit Values
Unit
Notes
min.
max.
Input high voltage
VIH
2.0
Vcc+0.3
V
1, 2
Input low voltage
VIL
– 0.3
0.8
V
1, 2
Output high voltage (IOUT = – 4.0 mA)
VOH
2.4
–
V
Output low voltage (IOUT = 4.0 mA)
VOL
–0.4
V
Input leakage current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V)
II(L)
– 5
5
A
Output leakage current
(DQ is disabled, 0 V < VOUT < VCC)
IO(L)
– 5
5
A
Symbol
Parameter & Test Condition
Max.
Unit
Note
-6
-7 / -7PC
ICC1
Operating Current
tRC = tRCMIN., tRC = tCKMIN.
Active-precharge command cycling, without
Burst Operation
1 bank operation
135
115
mA
7
ICC2P
Precharge Standby Current
in Power Down Mode
CS =VIH, CKE≤ VIL(max)
tCK = min.
2
mA
7
ICC2PS
tCK = Infinity
1
mA
7
ICC2N
Precharge Standby Current
in Non-Power Down Mode
CS =VIH, CKE≥ VIL(max)
tCK = min.
20
mA
ICC2NS
tCK = Infinity
10
mA
ICC3N
No Operating Current
tCK = min, CS = VIH(min)
bank ; active state ( 4 banks)
CKE
≥ VIH(MIN.)
25
mA
ICC3P
CKE
≤ VIL(MAX.)
(Power down mode)
33
mA
ICC4
Burst Operating Current
tCK = min
Read/Write command cycling
110
100
mA
7,8
ICC5
Auto Refresh Current
tCK = min
Auto Refresh command cycling
180
160
mA
7
ICC6
Self Refresh Current
Self Refresh Mode, CKE
≤ 0.2V
1.5
mA
L-version
0.8
mA
Notes:
7.These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and
tRC. Input signals are changed one time during tCK.
8.These parameter depend on output loading. Specified values are obtained with output open.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| V54C3128164VS | 制造商:MOSEL 制造商全称:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 |
| V54C3128164VT | 制造商:MOSEL 制造商全称:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 |
| V54C3128404VBGA | 制造商:MOSEL 制造商全称:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, BGA PACKAGE |
| V54C3128404VS | 制造商:MOSEL 制造商全称:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 |
| V54C3128404VT | 制造商:MOSEL 制造商全称:MOSEL 功能描述:128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 |
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