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参数资料
| 型号： | V58C2256404SHLH4I |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, PBGA60 |
| 封装： | ROHS COMPLIANT, MO-233, BGA-60 |
| 文件页数： | 29/60页 |
| 文件大小： | 1125K |
| 代理商： | V58C2256404SHLH4I |
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35
ProMOS TECHNOLOGIES
V58C2256(804/404/164)SH
V58C2256(804/404/164)SH Rev. 1.1 July 2010
IDD Max Specifications and Conditions
( VDDQ = 2.5V+ 0.2V, VDD = 2.5 +0.2V )
Conditions
Version
Symbol
-4
-5
-6
Unit
Operating current - One bank Active-Precharge; tRC=tRCmin; tCK= 100MHz for
DDR200, 133MHz for DDR266A & DDR266B, 166MHz for DDR333B, 200MHz for DDR400,
220MHz for DDR440; DQ,DM and DQS inputs changing twice per clock cycle; address and
control inputs changing once per clock cycle
IDD0
140
135
130
mA
Operating current - One bank operation; One bank open, BL=4
IDD1
155
150
145
mA
Precharge power-down standby current; All banks idle; power - down mode; CKE =
<VIL(max); tCK= 100MHz for DDR200, 133MHz for DDR266A & DDR266B, 166MHz for
DDR333B, 200MHz for DDR400, 220MHz for DDR440; Vin = Vref for DQ,DQS and DM
IDD2P
303030
mA
Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min);
tCK= 100MHz for DDR200, 133MHz for DDR266A & DDR266B, 166MHz for DDR333B,
200MHz for DDR400, 220MHz for DDR440; Address and other control inputs changing once
per clock cycle; Vin = Vref for DQ,DQS and DM
IDD2F
656565
mA
Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min);
tCK= 100MHz for DDR200, 133MHz for DDR266A & DDR266B, 166MHz for DDR333B,
200MHz for DDR400, 220MHz for DDR440; Address and other control inputs stable with
keeping >= VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM
IDD2Q
606060
mA
Active power - down standby current; one bank active; power-down mode; CKE=< VIL
(max); tCK= 100MHz for DDR200, 133MHz for DDR266A & DDR266B, 166MHz for
DDR333B, 200MHz for DDR400, 220MHz for DDR440; Vin = Vref for DQ,DQS and DM
IDD3P
404040
mA
Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active - pre-
charge; tRC=tRASmax; tCK= 100MHz for DDR200, 133MHz for DDR266A & DDR266B,
166MHz for DDR333B, 200MHz for DDR400, 220MHz for DDR440; DQ, DQS and DM in-
puts changing twice per clock cycle; address and other control inputs changing once per
clock cycle
IDD3N
115
mA
Operating current - burst read; Burst length = 2; reads; continuous burst; One bank active;
address and control inputs changing once per clock cycle; CL=2 at tCK = 100MHz for
DDR200, CL=2 at tCK = 133MHz for DDR266A, CL=2.5 at tCK = 133MHz for DDR266B,
CL=2.5 at tCK=166MHz for DDR333B, CL=2 at tCK = 200MHz for DDR400, CL=2.5 at tCK
= 220MHz for DDR440; 50% of data changing at every burst; lout = 0 m A
IDD4R
195
180
165
mA
Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active
address and control inputs changing once per clock cycle; CL=2 at tCK = 100MHz for
DDR200, CL=2 at tCK = 133MHz for DDR266A, CL=2.5 at tCK = 133MHz for DDR266B,
CL=2.5 at tCK=166MHz for DDR333B, CL=2 at tCK = 200MHz for DDR400, CL=2.5 at tCK
= 220MHz for DDR440; DQ, DM and DQS inputs changing twice per clock cycle, 50% of in-
put data changing at every burst
IDD4W
180
165
150
mA
Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100MHz, 10*tCK for
DDR266A & DDR266B at 133MHz, 12*tCK for DDR333B at 166MHz, 14*tCK for DDR400
at 200MHz, 16*tCK for DDR440 @220MHz; distributed refresh
IDD5
155
150
145
mA
Self refresh current; CKE =< 0.2V; External clock should be on; tCK = 100MHz for
DDR200, tCK = 133MHz for DDR266A & DDR266B, tCK = 166MHz for DDR333B, tCK =
200MHz for DDR400, tCK = 220MHz for DDR440
Self refresh current; (Low Power)
IDD6
(standard)
555
mA
(L)
2.5
mA
Operating current - Four bank operation; Four bank interleaving with BL=4
IDD7
295
mA
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