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参数资料
| 型号： | V58C2256404SHLM5I |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, PBGA60 |
| 封装： | GREEN, MO-233, BGA-60 |
| 文件页数： | 7/60页 |
| 文件大小： | 1125K |
| 代理商： | V58C2256404SHLM5I |
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ProMOS TECHNOLOGIES
V58C2256(804/404/164)SH
V58C2256(804/404/164)SH Rev. 1.1 July 2010
Precharge Operation
The Precharge command is used to deactivate the open row in a particular bank or the open row in all
banks. The bank (s) will be available for a subsequent row access a specified time (tRP) after the precharge
command is issued. Except in the case of concurrent auto precharge, where a READ or WRITE command
to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does
not violate any other timing parameters. Input A10 determines whether one or all banks are to be precharged,
and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0,
BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be acti-
vated prior to any READ or WRITE commands being issued to that bank. A Precharge command will be treat-
ed as NOP if there is no open row in that bank (idle state), or if the previously open row is already in the
process of precharging.
Auto Precharge Operation
The Auto Precharge operation can be issued by having column address A10 high when a Read or Write
command is issued. If A10 is low when a Read or Write command is issued, then normal Read or Write burst
operation is executed and the bank remains active at the completion of the burst sequence. When the Auto
Precharge command is activated, the active bank automatically begins to precharge at the earliest possible
moment during the Read or Write cycle once tRAS(min) is satisfied. This device supports concurrent auto pre-
charge if the command to the other bank does not interrupt the data transfer to the current bank.
Read with Auto Precharge
If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation
N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency pro-
grammed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until
the minimum precharge time (tRP) has been satisfied.
Read with Autoprecharge Timing
(CAS Latency = 2; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
D0
D1
D2
D3
Begin Autoprecharge
BA
ACT
R/w AP
NOP
CK, CK
Command
DQS
DQ
tRAS(min)
tRP(min)
Earliest Bank A reactivate
T9
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相关代理商/技术参数 |
参数描述 |
|---|---|
| V58C2256804S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
| V58C2256804SAT-5 | 制造商:Mosel Vitelic Corporation 功能描述:SDRAM, DDR, 32M x 8, 66 Pin, Plastic, TSSOP |
| V58C265164S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:64 Mbit DDR SDRAM 2.5 VOLT 4M X 16 |
| V58C265404S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4 |
| V58C265804S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8 |
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