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| 型号： | V59C1G01408QAUP25A |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, PBGA68 |
| 封装： | GREEN, FBGA-68 |
| 文件页数： | 68/79页 |
| 文件大小： | 1028K |
| 代理商： | V59C1G01408QAUP25A |
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70
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
IDD4W
Operating burst write current;
All banks open, Continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
mA
IDD4R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0 mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
mA
IDD5B
Burst refresh current;
tCK = tCK(IDD);
Refresh command at every tRFC(IDD) interval;
CKE is HIGH, CS is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
mA
IDD6
Self refresh current;
CK and CK at 0 V;
CKE
0.2 V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
mA
IDD7
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD(IDD) - 1 x tCK(IDD);
tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD),
tRCD = 1 x tCK(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R;
- Refer to the following pages for detailed timing conditions
mA
IDD specification parameters and test conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 6)
Symbol
Conditions
Max
Units
Notes
AC & DC operating conditions(cont'd)
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