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参数资料
| 型号： | V826616J24SAIX-D0 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 16M X 64 DDR DRAM MODULE, 0.65 ns, DMA184 |
| 封装： | GREEN, DIMM-184 |
| 文件页数： | 15/15页 |
| 文件大小： | 305K |
| 代理商： | V826616J24SAIX-D0 |
ProMOS TECHNOLOGIES
V826616J24SA
9
V826616J24SA Rev. 1.7 April 2006
DDR SDRAM module IDD spec table
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR333 (166MHz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR400B (200MHz, CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK, tRC=12*tCK, tRAS=8*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR400A (200MHz, CL=2.5) : tCK=5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=12*tCK, tRAS=8*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Symbol
D0 / D3
DDR400@CL=2.5,3
C0
DDR333@CL=2.5
B1
DDR266@CL=2
B0
DDR266@CL=2.5
Unit
IDD0
480
370
330
mA
IDD1
640
500
470
mA
IDD2P
120
12
mA
IDD2F
208
100
85
mA
IDD2Q
200
85
75
mA
IDD3P
140
130
mA
IDD3N
360
230
185
mA
IDD4R
1080
810
685
mA
IDD4W
1000
770
630
mA
IDD5
840
730
670
mA
IDD6
Normal
8
mA
Low power
4.8
mA
IDD7
1600
1410
1210
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
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