- 您现在的位置：买卖IC网 > PDF目录297710 > V826616J24SAIX-D0 (PROMOS TECHNOLOGIES INC) 16M X 64 DDR DRAM MODULE, 0.65 ns, DMA184 PDF资料下载
参数资料
| 型号： | V826616J24SAIX-D0 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 16M X 64 DDR DRAM MODULE, 0.65 ns, DMA184 |
| 封装： | GREEN, DIMM-184 |
| 文件页数： | 3/15页 |
| 文件大小： | 305K |
| 代理商： | V826616J24SAIX-D0 |
ProMOS TECHNOLOGIES
V826616J24SA
11
V826616J24SA Rev. 1.7 April 2006
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed
by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Write DQS High Level Width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
2.2
-
2.2
-
CLK
Write DQS Low Level Width
tDQSL
0.35
CLK
CLK to First Rising edge of DQS-In tDQSS
0.35
CLK
Data-In Setup Time to DQS-In (DQ
& DM)
tDS
0.72
1.25
0.72
1.25
0.75
1.25
0.75
1.25
0.75
1.25
ns
7
Data-in Hold Time to DQS-In (DQ
& DM)
tDH
0.40
-
0.40
-
0.45
-
0.5
-
0.5
-
ns
7
DQ & DM Input Pulse Width
tDIPW
0.40
-
0.40
-
0.45
-
0.5
-
0.5
-
ns
Read DQS Preamble Time
tRPRE
1.75
-
1.75
-
1.75
-
1.75
-
1.75
-
CLK
Read DQS Postamble Time
tRPST
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
CLK
Write DQS Preamble Setup Time tWPRES
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Write DQS Preamble Hold Time
tWPREH
0
-
0
-
0
-
0
-
0
-
CLK
Write DQS Postamble Time
tWPST
0.25
-
0.25
-
0.25
-
0.25
-
0.25
-
CLK
Mode Register Set Delay
tMRD
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Power Down Exit Time
tPDEX
2
-
2
-
2
-
2
-
2
-
ns
Exit Self Refresh to Non-Read
Command
tXSNR
1
-
1
-
1
-
1
-
1
-
ns
Exit Self Refresh to Read Com-
mand
tXSRD
200
-
200
-
200
-
75
-
75
-
CLK
8
Average Periodic Refresh Interval
tREFI
200
-
200
-
200
-
200
-
200
-
us
Parameter
Sym-
bol
(DDR400A)
D0
(DDR400B)
D3
(DDR333)
C0
(DDR266A)
B1
(DDR266B)
B0
Unit Note
Min
Max Min
Max
相关PDF资料 |
PDF描述 |
|---|---|
| V826632K24S | 2.5 VOLT 32M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE |
| V827332U04S | 2.5 VOLT 32M x 72 HIGH PERFORMANCE REGISTERED ECC DDR SDRAM MODULE |
| V827432K24SAEX-B1 | 32M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| V827432K24S | 2.5 VOLT 32M x 72 HIGH PERFORMANCE UNBUFFERED ECC DDR SDRAM MODULE |
| V85ECADBFREQ | VCXO, CLOCK, 1.5 MHz - 200 MHz, HCMOS OUTPUT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| V826632B24S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:256 MB 200-PIN DDR UNBUFFERED SODIMM 2.5 VOLT 32M x 64 |
| V826632G24S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:256 MB 200-PIN DDR UNBUFFERED SODIMM 2.5 VOLT 32M x 64 |
| V826632K24S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:2.5 VOLT 32M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE |
| V826664G24S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:512 MB 200-PIN DDR UNBUFFERED SODIMM 2.5 VOLT 64M x 64 |
| V826664K24S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:2.5 VOLT 64M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE |
发布紧急采购，3分钟左右您将得到回复。