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参数资料
| 型号： | V827432K24S |
| 厂商： | Mosel Vitelic, Corp. |
| 英文描述： | 2.5 VOLT 32M x 72 HIGH PERFORMANCE UNBUFFERED ECC DDR SDRAM MODULE |
| 中文描述： | 2.5伏32M × 72配置高性能无缓冲ECC DDR SDRAM内存模块 |
| 文件页数： | 14/14页 |
| 文件大小： | 211K |
| 代理商： | V827432K24S |
MOSEL VITELIC
V827432K24S
9
V827432K24S Rev.1.2 September 2002
DDR SDRAM IDD SPEC TABLE
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Symbol
A1
PC1600@CL=2
B0
PC2100B@CL=2.5
B1
PC2100A@CL=2
C0
PC2100A@CL=2.5
Unit
IDD0
680
870
1060
mA
IDD1
850
1100
1280
mA
IDD2P
30
mA
IDD2F
220
250
280
mA
IDD2Q
140
170
190
mA
IDD3P
210
290
370
mA
IDD3N
360
460
550
mA
IDD4R
1150
1400
1700
mA
IDD4W
1180
1350
1600
mA
IDD5
1600
1700
1800
mA
IDD6
Normal
30
mA
Low power
15
mA
IDD7
1980
2580
3180
mA
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