- 您现在的位置：买卖IC网 > PDF目录225500 > V827432U24SAIL-C0 (PROMOS TECHNOLOGIES INC) 32M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 PDF资料下载
参数资料
| 型号： | V827432U24SAIL-C0 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封装： | DIMM-184 |
| 文件页数： | 3/16页 |
| 文件大小： | 434K |
| 代理商： | V827432U24SAIL-C0 |
ProMOS TECHNOLOGIES
V827432U24SA
11
V827432U24SA Rev. 1.2 April 2006
AC Characteristics (cont.)
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed
by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM
Absolute Maximum Ratings
Note: Operation at above absolute maximum rating can adversely affect device reliability
CLK to First Rising edge of DQS-In tDQSS
0.35
0.45
-
0.75
1.25
0.75
1.25
CLK
Data-In Setup Time to DQS-In (DQ
& DM)
tDS
0.72
1.25
0.72
1.25
0.45
-
0.5
-
0.5
-
ns
7
Data-in Hold Time to DQS-In (DQ
& DM)
tDH
0.40
-
0.40
-
1.75
-
0.5
-
0.5
-
ns
7
DQ & DM Input Pulse Width
tDIPW
1.75
-
1.75
-
0.9
1.1
1.75
-
1.75
-
ns
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
0.4
0.6
0.9
1.1
0.9
1.1
CLK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
0
-
0.4
0.6
0.4
0.6
CLK
Write DQS Preamble Setup Time tWPRES
0
-
0
-
0.25
-
0
-
0
-
CLK
Write DQS Preamble Hold Time
tWPREH 0.25
-
0.25
-
0.4
0.6
0.25
-
0.25
-
CLK
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
2
-
0.4
0.6
0.4
0.6
CLK
Mode Register Set Delay
tMRD
2
-
2
-
10
-
2
-
2
-
CLK
Power Down Exit Time
tPDEX
1
-
1
-
75
-
10
-
10
-
ns
Exit Self Refresh to Non-Read
Command
tXSNR
200
-
200
-
200
-
75
-
75
-
ns
Exit Self Refresh to Read Com-
mand
tXSRD
200
-
200
-
200
-
200
-
200
-
CLK
8
Average Periodic Refresh Interval
tREFI
-
7.8
-
7.8
-
7.8
-
7.8
-
7.8
us
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on Any Pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD relative to VSS
VDD
-0.5 ~ 3.6
V
Voltage on VDDQ relative to VSS
VDDQ
-0.5 ~ 3.6
V
Output Short Circuit Current
IOS
50
mA
Power Dissipation
PD
11
W
Soldering Temperature Time
TSOLDER
260 10
°C Sec
Parameter
Sym-
bol
DDR400A
D0
DDR400B
D3
DDR333
C0
DDR266A
B1
DDR266B
B0
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
相关PDF资料 |
PDF描述 |
|---|---|
| V827464K24SATGD3 | 64M X 72 DDR DRAM MODULE, 0.65 ns, DMA184 |
| V850E1 | 32-Bit Microprocessor Core |
| V902-FREQ | VCXO, CLOCK, 65 MHz - 200 MHz, LVDS OUTPUT |
| V903-FREQ | VCXO, CLOCK, 200 MHz - 730 MHz, LVDS OUTPUT |
| VB-24STBU | POWER/SIGNAL RELAY, DPDT, MOMENTARY, 0.022A (COIL), 24VDC (COIL), 530mW (COIL), 5A (CONTACT), 150VDC (CONTACT), THROUGH HOLE-STRAIGHT MOUNT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| V827464K24S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:2.5 VOLT 64M x 72 HIGH PERFORMANCE UNBUFFERED ECC DDR SDRAM MODULE |
| V827464N24S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:2.5 VOLT 64M x 72 HIGH PERFORMANCE REGISTERED ECC DDR SDRAM MODULE |
| V8290 | 制造商:Visual Effects 功能描述:Mini Strobe Light 制造商:VISUAL EFFECTS 功能描述:MINI STROBE LIGHT |
| V82MA3A | 功能描述:压敏电阻 82V 40A 120pF RoHS:否 制造商:EPCOS 产品:MLV 电压额定值 DC:22 V 电压额定值 AC:17 V 钳位电压:50 V 直径: 峰值浪涌电流:30 A 浪涌能量额定值:75 mJ 电容:74.2 pF 工作温度范围:- 55 C to + 125 C 安装:SMD/SMT 封装:Reel |
| V82MA3B | 功能描述:压敏电阻 82V 40A 120pF RoHS:否 制造商:EPCOS 产品:MLV 电压额定值 DC:22 V 电压额定值 AC:17 V 钳位电压:50 V 直径: 峰值浪涌电流:30 A 浪涌能量额定值:75 mJ 电容:74.2 pF 工作温度范围:- 55 C to + 125 C 安装:SMD/SMT 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。