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参数资料
| 型号： | V827464N24SCSL-D3 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.65 ns, DMA184 |
| 封装： | DIMM-184 |
| 文件页数： | 17/17页 |
| 文件大小： | 370K |
| 代理商： | V827464N24SCSL-D3 |
ProMOS TECHNOLOGIES
V827464N24SC
9
V827464N24SC Rev. 1.2 April 2006
DDR SDRAM IDD SPEC TABLE
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR333 (166MHz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR400B (200MHz, CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK, tRC=12*tCK, tRAS=8*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR400A (200MHz, CL=2.5) : tCK=5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=12*tCK, tRAS=8*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Symbol
D0 / D3
PC3200A@
CL=3
C0
PC2700A@
CL=2.5
Unit
IDD0
1100
990
mA
IDD1
1340
1260
mA
IDD2P
500
450
mA
IDD2F
450
405
mA
IDD2Q
350
396
mA
IDD3P
500
450
mA
IDD3N
800
720
mA
IDD4R
2300
2070
mA
IDD4W
2100
1890
mA
IDD5
1900
1800
mA
IDD6
Normal
54
mA
Low power
33
mA
IDD7
3200
3150
mA
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