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参数资料
| 型号： | V85C2256164SAS8 |
| 厂商： | MOSEL-VITELIC |
| 元件分类： | DRAM |
| 英文描述： | 16M X 16 DDR DRAM, 0.8 ns, PBGA60 |
| 封装： | 0.80 X 1 MM PITCH, SOC, BGA-60 |
| 文件页数： | 1/61页 |
| 文件大小： | 814K |
| 代理商： | V85C2256164SAS8 |
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MOSEL VITELIC
1
V58C2256(804/404/164)S
HIGH PERFORMANCE
2.5 VOLT 256 Mbit DDR SDRAM
4 BANKS X 8Mbit X 8 (804)
4 BANKS X 4Mbit X 16 (164)
4 BANKS X 16Mbit X 4 (404)
PRELIMINARY
V58C2256(804/404/164)S Rev.1.4 October 2002
67
75
8
DDR333B
DDR266A
DDR266B
DDR200
Clock Cycle Time (tCK2)
7.5 ns
7.5ns
10 ns
Clock Cycle Time (tCK2.5)
6 ns
7ns
7.5 ns
8 ns
System Frequency (fCK max)
166 MHz
143 MHz
133 MHz
125 MHz
Features
■ High speed data transfer rates with system
frequency up to 166 MHz
■ Data Mask for Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2, 2.5
■ Programmable Wrap Sequence: Sequential
or Interleave
■ Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■ Automatic and Controlled Precharge Command
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 8192 cycles/64 ms
■ Available in 66-pin 400 mil TSOP or 60 Ball SOC
BGA
■ SSTL-2 Compatible I/Os
■ Double Data Rate (DDR)
■ Bidirectional Data Strobe (DQS) for input and
output data, active on both edges
■ On-Chip DLL aligns DQ and DQs transitions with
CK transitions
■ Differential clock inputs CK and CK
■ Power Supply 2.5V ± 0.2V
■ QFC options for FET control. x4 parts.
*Note: DDR 333B Supports PC2700 module with 2.5-3-3 timing
DDR 266A Supports PC2100 module with 2-2-2 timing
DDR 266B Supports PC2100 module with 2.5-3-3 timing
DDR 200 Supports PC1600 module with 2-2-2 timing
Description
The V58C2256(804/404/164)S is a four bank
DDR DRAM organized as 4 banks x 8Mbit x 8 (804),
4 banks x 4Mbit x 16 (164), or 4 banks x 16Mbit x 4
(404). The V58C2256(804/404/164)S achieves high
speed data transfer rates by employing a chip archi-
tecture that prefetches multiple bits and then syn-
chronizes the output data to a system clock.
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are ocurring on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
CK Cycle Time (ns)
Power
Temperature
Mark
JEDEC 66 TSOP II
60 SOC BGA
-6
-7
-75
-8
Std.
L
0°C to 70°C
Blank
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