- 您现在的位置：买卖IC网 > PDF目录202175 > V85C2256164SAS8 (MOSEL-VITELIC) 16M X 16 DDR DRAM, 0.8 ns, PBGA60 PDF资料下载
参数资料
| 型号： | V85C2256164SAS8 |
| 厂商： | MOSEL-VITELIC |
| 元件分类： | DRAM |
| 英文描述： | 16M X 16 DDR DRAM, 0.8 ns, PBGA60 |
| 封装： | 0.80 X 1 MM PITCH, SOC, BGA-60 |
| 文件页数： | 2/61页 |
| 文件大小： | 814K |
| 代理商： | V85C2256164SAS8 |
第1页当前第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页
10
V58C2256(804/404/164)S Rev. 1.4 October 2002
MOSEL VITELIC
V58C2256(804/404/164)S
Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising
edge of the clock. The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0 and
BA1) are supported. The Bank Activate command must be applied before any Read or Write operation can
be executed. The delay from the Bank Activate command to the first Read or Write command must meet or
exceed the minimum RAS to CAS delay time (tRCD min). Once a bank has been activated, it must be pre-
charged before another Bank Activate command can be applied to the same bank. The minimum time interval
between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay
time (tRRD min).
Bank Activation Timing
Read Operation
With the DLL enabled, all devices operating at the same frequency within a system are ensured to have
the same timing relationship between DQ and DQS relative to the CK input regardless of device density, pro-
cess variation, or technology generation.
The data strobe signal (DQS) is driven off chip simultaneously with the output data (DQ) during each read
cycle. The same internal clock phase is used to drive both the output data and data strobe signal off chip to
minimize skew between data strobe and output data. This internal clock phase is nominally aligned to the
input differential clock (CK, CK) by the on-chip DLL. Therefore, when the DLL is enabled and the clock fre-
quency is within the specified range for proper DLL operation, the data strobe (DQS), output data (DQ), and
the system clock (CK) are all nominally aligned.
Since the data strobe and output data are tightly coupled in the system, the data strobe signal may be de-
layed and used to latch the output data into the receiving device. The tolerance for skew between DQS and
DQ (tDQSQ) is tighter than that possible for CK to DQ (tAC) or DQS to CK (tDQSCK).
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
(CAS Latency = 2; Burst Length = Any)
tRRD(min)
tRP(min)
tRC
tRCD(min)
Begin Precharge Bank A
CK, CK
BA/Address
Command
Bank/Col
Read/A
Bank/Row
Activate/A
Activate/B
Pre/A
Bank/Row
Activate/A
Bank
Bank/Row
tRAS(min)
相关PDF资料 |
PDF描述 |
|---|---|
| V85FACCBAFREQ | VCXO, CLOCK, 1.5 MHz - 200 MHz, HCMOS OUTPUT |
| V85GBAAA155.520MHZ | VCXO, CLOCK, 155.52 MHz, PECL OUTPUT |
| V85GAABA001.500MHZ | VCXO, CLOCK, 1.5 MHz, PECL OUTPUT |
| V85GABAA155.520MHZ | VCXO, CLOCK, 155.52 MHz, PECL OUTPUT |
| V85GABAB155.520MHZ | VCXO, CLOCK, 155.52 MHz, LVDS OUTPUT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| V85ES00C-GZCY8-1Z1-XPN1 | 制造商:Carling Technologies 功能描述:V-SERIES ROCKER SWITCH - Bulk |
| V85MLA1210 | 制造商:LITTELFUSE 制造商全称:Littelfuse 功能描述:Multilayer Transient Voltage Surge Suppressors |
| V85MLA1210A | 功能描述:压敏电阻 85V 250A 260pF RoHS:否 制造商:EPCOS 产品:MLV 电压额定值 DC:22 V 电压额定值 AC:17 V 钳位电压:50 V 直径: 峰值浪涌电流:30 A 浪涌能量额定值:75 mJ 电容:74.2 pF 工作温度范围:- 55 C to + 125 C 安装:SMD/SMT 封装:Reel |
| V85MLA1210H | 功能描述:压敏电阻 85V 250A 260pF RoHS:否 制造商:EPCOS 产品:MLV 电压额定值 DC:22 V 电压额定值 AC:17 V 钳位电压:50 V 直径: 峰值浪涌电流:30 A 浪涌能量额定值:75 mJ 电容:74.2 pF 工作温度范围:- 55 C to + 125 C 安装:SMD/SMT 封装:Reel |
| V85MLA1210H | 制造商:Littelfuse 功能描述:Metal Oxide Varistor (MOV) |
发布紧急采购，3分钟左右您将得到回复。