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参数资料
| 型号： | VME64E07P01 |
| 厂商： | Vector Electronics |
| 文件页数： | 4/7页 |
| 文件大小： | 0K |
| 描述： | BACKPLANE VME 64X7SLOT J1/J2/P0 |
| 标准包装： | 1 |
| 系列： | VME |
| 面板单元： | 6U |
| 通道数： | 7 |
| 接口： | VME J1/J2/J0 |
| 连接器间距： | 0.800"（20.32mm） |
VECTOR ELECTRONICS & TECHNOLOGY, INC .
VMEbus Signal Descriptions
Signal Name
A01 - A31
BR0* - BR3*
D00-D31
DS0*, DS1*
DTACK*
GA0* - GA4*
Description
Address lines [A01 - A31] carry a binary address.
The address modifier code [AM0 - AM5] is a 'tag' that indicates the
type of VMEbus cycle in progress.
The bus grant signals [BG0IN* - BG3IN* and BG0OUT* -
BG3OUT*] are part of the bus grant daisy chain and are driven by
arbiters and requesters. The slot 01 arbiter asserts a bus grant in
response to a bus request on the same level [BR0* - BR3*]. The bus
grant daisy-chain starts at the slot 01 system controller and
propagates from module to module until it reaches the module that
initially requested the bus. Each VMEbus module has a bus grant
input and a bus grant output. They are standard totem-pole class
signals.
Bus requests [BR0* - BR3*] are asserted by a requester whenever
its master or interrupt han-dler needs the bus. Before accepting the
bus, the master waits until the arbiter grants the bus by way of the
bus grant daisy-chain [BG0IN* - BG3IN*]. They are open-collector
class signals.
Data bus [D00-D31] is driven by masters, slaves or interrupters.
These are bi-directional sig-nals and are used for data transfers.
Different portions of the data bus are used de-pending upon the state
of DS0*, DS1*, A01 and LWORD* pins. They are standard three-
state signals. The data lines can also be used to transfer a portion of
the address during MD32, MBLT and 2eVME cycles.
Data strobes DS0* and DS1* are driven by masters and interrupt
handlers. These sig-nals serve not only to qualify data, but also to
indicate the size and position of the data transfer. When combined
with LWORD* and A01, the data strobes indicate the size and type
of data transfer. DS0* - DS1* are high current three-state class
signals.
Data transfer acknowledge [DTACK*] is driven by slaves or
interrupters. During write cycles DTACK* is asserted by a slave
after it has latched data. During read and inter-rupt acknowledge
cycles, DTACK* is asserted by a slave after data is placed onto the
bus. DTACK* can be an open-collector or a high current three-state
class signal.
The geographical address [GA0*-GA4*] is a binary code that
indicates the slot number of the backplane. They are open collector
signals, and were added to the 160 pin P1/J1 connector in the
VME64x specification.
Page 4
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