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参数资料
| 型号： | VME64E07P01 |
| 厂商： | Vector Electronics |
| 文件页数： | 6/7页 |
| 文件大小： | 0K |
| 描述： | BACKPLANE VME 64X7SLOT J1/J2/P0 |
| 标准包装： | 1 |
| 系列： | VME |
| 面板单元： | 6U |
| 通道数： | 7 |
| 接口： | VME J1/J2/J0 |
| 连接器间距： | 0.800"（20.32mm） |
VECTOR ELECTRONICS & TECHNOLOGY, INC .
The reserved/bused [RsvB] signal should not be used. VME64x
RsvB
RsvU
RETRY*
SERA, SERB
SERCLK, SERDAT*
SYSCLK
SYSFAIL*
SYSRESET*
backplanes must bus and terminate this signal. It was added to the
160 pin P1/J1 connector in the VME64x specification.
The reserved/unbused [RsvU] signal should not be used. VME64x
backplanes must not bus or terminate this signal. It was added to the
160 pin P1/J1 connector in the VME64x specification.
[RETRY*], together with [BERR*], can be asserted by a slave to
postpone a data transfer. The master must then attempt the cycle
again at a later time. The retry cycle prevents deadlock (deadly
embrace) conditions in bus-to-bus links and sec-ondary buses.
RETRY* is a standard three-state signal. The [RETRY*] signal was
added in the ANSI/VITA 1-1994 (VME64) version of the bus spec-
ification. This pin was RESERVED in earlier versions. However,
boards that support [RETRY*] should work just fine with older
backplanes, as they were required to bus and terminate this signal
line.
The [SERA] and [SERB] signals are used for an (optional) serial
bus such as the AUTOBAHN (IEEE 1394) or VMSbus. Under the
ANSI/VITA 1-1994 (VME64) bus specification, these pins can be
used for any user defined serial bus. Earlier versions of the VMEbus
specification defined these pins as [SERCLK] and [SERDAT*],
which were originally intended for a serial bus called VMSbus.
However, they were rarely used for that purpose.
The [SERCLK] and [SERDAT*] signals were made obsolete under
the ANSI/VITA 1-1994 (VME64) bus specification. Refer to
[SERA] and [SERB] for more details.
16 MHz utility clock [SYSCLK] is driven by the slot 01 system
controller. This clock can be used for any purpose, and has no
timing relationship to other VMEbus signals. SYSCLK* is a high
current totem-pole class signal.
System fail [SYSFAIL*] can be asserted or monitored by any
module. It indicates that a failure has occurred in the system.
Implementation of [SYSFAIL*] is user de-fined, and its use is
optional. SYSFAIL* is an open-collector class signal.
System reset [SYSRESET*] can be driven by any module and
indicates that a reset (such as power-up) is in progress.
SYSRESET* is an open-collector class signal.
Pins that are user defined [specified as 'UsrDef' or 'UD'] can be
specified by the user. Generally, they are routed directly through the
backplane so that they can be connected to cables or to rear I/O
transition modules.
Page 6
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相关代理商/技术参数 |
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